知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

23 records (took 0.014 seconds)

    PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A UNIFORM DEPTH TUNGSTEN RECESS TECHNIQUE
    5.
    发明申请
    PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A UNIFORM DEPTH TUNGSTEN RECESS TECHNIQUE 有权
    集成电路制造工艺，包括均匀深度浸渍技术

    公开(公告)号：US20170012105A1

    公开(公告)日：2017-01-12

    申请号：US15273777

    申请日：2016-09-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

    Inventor： QING LIU ,  RUILONG XIE ,  CHUN-CHEN YEH

    IPC: H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49

    CPC classification number: H01L29/42376 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78

    Abstract: Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.

    Abstract translation: 从预金属层去除虚拟门以产生具有第一长度的第一开口和第二开口（具有长于第一长度的第二长度）。 用于金属栅电极的功函数金属设置在第一和第二开口中。 沉积钨以填充第一开口并保形地排列第二开口，从而留下第三个开口。 钨层的厚度基本上等于第一开口的长度。 第三个开口填充绝缘材料。 然后使用干蚀刻将钨从第一和第二开口凹入到与金属前层的顶表面基本相同的深度以完成金属栅电极。 然后在凹槽操作之后留下的开口填充有在包括金属栅电极的栅堆叠上形成盖的电介质材料。

    SEMICONDUCTOR DEVICE INCLUDING STRESS LAYER ADJACENT CHANNEL AND RELATED METHODS
    9.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING STRESS LAYER ADJACENT CHANNEL AND RELATED METHODS 审中-公开
    包括应力层相邻通道的半导体器件及相关方法

    公开(公告)号：US20150102410A1

    公开(公告)日：2015-04-16

    申请号：US14050666

    申请日：2013-10-10

    Applicant: GLOBALFOUNDRIES INC ,  STMicroelectronics, Inc.

    Inventor： QING LIU ,  Xiuyu Cai ,  Ruilong Xie

    IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

    CPC classification number: H01L29/6653 ,  H01L29/66515 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7846 ,  H01L29/78684

    Abstract: A method for making a semiconductor device may include forming a gate on a semiconductor layer, forming sidewall spacers adjacent the gate, and forming raised source and drain regions defining a channel in the semiconductor layer under the gate. The raised source and drain regions may be spaced apart from the gate by the sidewall spacers. The method may further include removing the sidewall spacers to expose the semiconductor layer between the raised source and drain regions and the gate, and forming a stress layer overlying the gate and the raised source and drain regions. The stress layer may contact the semiconductor layer between the raised source and drain regions and the gate.

    Abstract translation: 制造半导体器件的方法可以包括在半导体层上形成栅极，在栅极附近形成侧壁间隔物，以及形成在栅极下方的半导体层中限定沟道的凸起的源极和漏极区域。 升高的源极和漏极区域可以通过侧壁间隔物与栅极间隔开。 该方法还可以包括移除侧壁间隔物以暴露凸起的源极和漏极区域和栅极之间的半导体层，并且形成覆盖栅极和升高的源极和漏极区域的应力层。 应力层可以接触凸起的源极和漏极区域与栅极之间的半导体层。

Patent Agency Ranking