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    Semiconductor assembly and method of manufacture
    1.
    发明授权
    Semiconductor assembly and method of manufacture 有权

    公开(公告)号：US09997507B2

    公开(公告)日：2018-06-12

    申请号：US13950736

    申请日：2013-07-25

    Applicant: General Electric Company

    Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  Rui Zhou ,  Peter Almern Losee

    IPC: H01L29/76 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/02

    CPC classification number: H01L27/0248 ,  H01L2924/0002

    Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

    METHOD AND SYSTEM FOR TRANSIENT VOLTAGE SUPPRESSORS
    2.
    发明申请
    METHOD AND SYSTEM FOR TRANSIENT VOLTAGE SUPPRESSORS 有权
    瞬态电压抑制器的方法和系统

    公开(公告)号：US20130328064A1

    公开(公告)日：2013-12-12

    申请号：US13967886

    申请日：2013-08-15

    Applicant: GENERAL ELECTRIC COMPANY

    Inventor： Avinash Srikrishnan Kashyap ,  David Mulford Shaddock ,  Emad Andarawis Andarawis ,  Peter Micah Sandvik ,  Stephen Daley Arthur ,  Vinayak Tilak

    IPC: H01L21/56 ,  H01L29/16

    CPC classification number: H01L21/56 ,  H01L23/3185 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/861 ,  H01L29/8618 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.

    Abstract translation: 提供了形成碳化硅瞬态电压抑制器（TVS）组件的方法和用于瞬态电压抑制器（TVS）组件的系统。 TVS组件包括台面结构中的半导体管芯，其包括具有第一极性的导电率的第一宽带隙半导体的第一层，具有第二极导电率的第一或第二宽带隙半导体的第二层 极性与第一层电接触，其中第二极性不同于第一极性。 TVS组件还包括具有与第二层电接触的第一极性的导电性的第一，第二或第三宽带隙半导体的第三层。 相对于具有第一极性的导电性的层，具有第二极性的导电性的层被轻掺杂。

    SOLID STATE PHOTO MULTIPLIER DEVICE
    5.
    发明申请
    SOLID STATE PHOTO MULTIPLIER DEVICE 审中-公开
    固态照相机设备

    公开(公告)号：US20150285942A1

    公开(公告)日：2015-10-08

    申请号：US14244979

    申请日：2014-04-04

    Applicant: General Electric Company

    Inventor： Stanislav Ivanovich Soloviev ,  Peter Micah Sandvik ,  Sergei Ivanovich Dolinsky ,  Cheng-Po Chen ,  Helene Claire Climent ,  Sabarni Palit

    IPC: G01V5/08 ,  E21B47/00

    CPC classification number: G01V5/08 ,  E21B47/00 ,  G01T1/2006 ,  G01T1/2018 ,  G01T1/24 ,  G01T1/248 ,  G01V5/04

    Abstract: A method and an apparatus for detecting photons are disclosed. The apparatus includes a solid state photo multiplier device having a plurality of microcells that have a band gap greater than about 1.7 eV at 25° C. The solid state photo multiplier device further includes an integrated quenching device and a thin film coating associated with each of the microcells. The solid state photo multiplier device disclosed herein operates in a temperature range of about −40° C. to about 275° C.

    Abstract translation: 公开了一种用于检测光子的方法和装置。 该装置包括具有在25℃下具有大于约1.7eV的带隙的多个微小区的固态光电倍增器装置。固态光电倍增器装置还包括集成的淬火装置和与每个微电池相关联的薄膜涂层 微电池。 本文公开的固态光电倍增器装置在约-40℃至约275℃的温度范围内操作。

    OVER-VOLTAGE PROTECTION OF GALLIUM NITRIDE SEMICONDUCTOR DEVICES
    6.
    发明申请
    OVER-VOLTAGE PROTECTION OF GALLIUM NITRIDE SEMICONDUCTOR DEVICES 有权
    氮化镓半导体器件的过电压保护

    公开(公告)号：US20150001551A1

    公开(公告)日：2015-01-01

    申请号：US13931363

    申请日：2013-06-28

    Applicant: General Electric Company

    Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  Rui Zhou

    IPC: H01L27/02 ,  H01L21/8232 ,  H01L29/267 ,  H01L27/06

    CPC classification number: H01L27/0248 ,  H01L21/8213 ,  H01L21/8232 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0617 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/7786

    Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon carbide (SiC), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

    Abstract translation: 提出了一种单片集成半导体组件。 半导体组件包括包含碳化硅（SiC）的衬底，并且在衬底上制造氮化镓（GaN）半导体器件。 半导体组件还包括在衬底中或衬底上制造的至少一个瞬态电压抑制器（TVS）结构，其中TVS结构与GaN半导体器件电接触。 当跨越GaN半导体器件的施加电压大于阈值电压时，TVS结构被配置为以穿通模式，雪崩模式或其组合工作。 还提出了制造单片集成半导体组件的方法。

    Silicon-carbide MOSFET cell structure and method for forming same
    7.
    发明授权
    Silicon-carbide MOSFET cell structure and method for forming same 有权
    碳化硅MOSFET单元结构及其形成方法

    公开(公告)号：US08507986B2

    公开(公告)日：2013-08-13

    申请号：US13740758

    申请日：2013-01-14

    Applicant: General Electric Company

    Inventor： Stephen Daley Arthur ,  Kevin Sean Matocha ,  Peter Micah Sandvik ,  Zachary Matthew Stum ,  Peter Almren Losee ,  James Jay McMahon

    IPC: H01L29/76 ,  H01L21/332

    CPC classification number: H01L27/088 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802

    Abstract: In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.

    Abstract translation: 在一个实施例中，本发明包括一个包含单个MOSFET单元的MOSFET。 每个单元包括形成在井内的U形孔（P型）和两个平行的源（N型）。 在多个位置连接多个源极（掺杂N）源极。 两个梯级之间的区域包括一个主体（P型）。 这些特征形成在形成在N型衬底上的N型外延层上。 联系人跨越并接触许多源级和身体。 栅极氧化物和栅极接触覆盖第一阱的支腿和第二相邻阱的支路，响应于栅极电压而反转导电性。 MOSFET包括多个这些单元以获得期望的低通道电阻。 在制造过程的几个状态下使用自对准技术形成单元区域。

    Method and system for a semiconductor device with integrated transient voltage suppression
    10.
    发明授权
    Method and system for a semiconductor device with integrated transient voltage suppression 有权
    具有集成瞬态电压抑制的半导体器件的方法和系统

    公开(公告)号：US09508841B2

    公开(公告)日：2016-11-29

    申请号：US13957115

    申请日：2013-08-01

    Applicant: General Electric Company

    Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  James Jay McMahon ,  Ljubisa Dragoljub Stevanovic

    IPC: H01L29/78 ,  H01L29/16 ,  H01L29/74 ,  H01L27/02 ,  H01L29/861 ,  H01L29/739

    CPC classification number: H01L27/0617 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0255 ,  H01L29/1608 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7424 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/861

    Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

    Abstract translation: 提供功率晶体管组件和操作组件的方法。 所述功率晶体管组件包括在单个半导体衬底上的集成瞬态电压抑制，并且包括由宽带隙材料形成的晶体管，所述晶体管包括栅极端子，源极端子和漏极端子，所述晶体管还包括预定的最大允许量 栅极电压值以及由宽带隙材料形成的瞬态电压抑制（TVS）器件，所述TVS器件由所述晶体管形成为单个半导体器件，所述TVS器件电耦合到所述晶体管的至少一个栅极和 源极端子和漏极和源极端子，TVS器件包括被选择为大于预定的最大允许栅极电压值的击穿电压限制。

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