公开(公告)号：US07498962B2

公开(公告)日：2009-03-03

申请号：US11618644

申请日：2006-12-29

Applicant: Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alvin Storvik ,  Paul Highley ,  Douglas R. Holberg

Inventor： Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alvin Storvik ,  Paul Highley ,  Douglas R. Holberg

IPC: H03M1/00

CPC classification number: G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method for converting analog data to digital data includes operating an analog-to-digital data converter in a tracking mode to sample an input signal and in a convert mode to convert the sampled input signal after sampling to a digital signal. The analog-to-digital data converter is controlled with a controller to operate in different modes of operation by providing at least one step wherein the tracking mode of operation is controlled to initiate at a predetermined time to begin the sampling operation.

Abstract translation: 一种将模拟数据转换为数字数据的方法包括以跟踪模式操作模拟数字数据转换器，以对输入信号进行采样，并以转换模式将采样后的采样输入信号转换为数字信号。 模拟数字数据转换器由控制器控制，以通过提供至少一个步骤操作在不同的操作模式，其中跟踪操作模式被控制以在预定时间开始以开始采样操作。

公开(公告)号：US07411538B1

公开(公告)日：2008-08-12

申请号：US11695002

申请日：2007-03-31

Applicant: Douglas S. Piasecki

Inventor： Douglas S. Piasecki

IPC: H03M1/38

CPC classification number: H03M1/0607 ,  H03M1/123 ,  H03M1/46 ,  H03M1/662 ,  H03M1/68 ,  H03M1/802

Abstract: A circuit includes a successive approximation register A/D converter for performing analog to digital conversions. The register has a ground pin and a ground sense pin. The ground sense pin is connected to a ground port of the circuit. A multiplexer connects the ground sense pin of the successive approximation register A/D converter to one of a plurality of I/O ports of the circuit package. A switch selectively connects the ground sense pin of the successive approximation register A/D converter to the ground port.

Abstract translation: 电路包括用于执行模数转换的逐次逼近寄存器A / D转换器。 寄存器具有接地引脚和接地检测引脚。 接地感测引脚连接到电路的接地端口。 多路复用器将逐次逼近寄存器A / D转换器的接地检测引脚连接到电路封装的多个I / O端口之一。 开关选择性地将逐次逼近寄存器A / D转换器的接地检测引脚连接到接地端口。

公开(公告)号：US06529152B1

公开(公告)日：2003-03-04

申请号：US09901845

申请日：2001-07-09

Applicant: Douglas S. Piasecki ,  Ka Y. Leung

Inventor： Douglas S. Piasecki ,  Ka Y. Leung

IPC: H03N166

CPC classification number: H03M1/682 ,  H03M1/46 ,  H03M1/765

Abstract: A digital-to-analog converter having a semiconductor resistor strip with plural voltage taps. One voltage tap formed of the semiconductor material defines a nonzero reference voltage for the converter. An auto-zeroing amplifier is utilized to charge a coupling capacitor to the nonzero reference voltage. In the conversion process, the analog voltages at the other voltage taps of the resistor strip are selected via a switch arrangement and coupled to the coupling capacitor. The linearity of the digital-to-analog converter is thus more independent of parasitic resistances that may be formed in the ground connection to the resistor string.

Abstract translation: 具有具有多个电压抽头的半导体电阻条的数 - 模转换器。 由半导体材料形成的一个电压抽头为转换器定义非零参考电压。 利用自动归零放大器将耦合电容器充电到非零参考电压。 在转换过程中，电阻条的其他电压抽头上的模拟电压经由开关装置选择并耦合到耦合电容器。 因此，数 - 模转换器的线性度与在与电阻串的接地连接中可能形成的寄生电阻更独立。

公开(公告)号：US06507215B1

公开(公告)日：2003-01-14

申请号：US09837918

申请日：2001-04-18

Applicant: Douglas S. Piasecki ,  Alvin C. Storvik, II

Inventor： Douglas S. Piasecki ,  Alvin C. Storvik, II

IPC: G06F738

CPC classification number: G06F13/4072

Abstract: A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals.

Abstract translation: 集成电路的引脚接口。 引脚接口包括用于处理数字信号的逻辑门和用于承载模拟信号的模拟线。 引脚接口包括用于在配置为承载模拟信号时禁用数字电路的电路。

公开(公告)号：US06456220B1

公开(公告)日：2002-09-24

申请号：US09595959

申请日：2000-06-19

Applicant: Ka Y. Leung ,  Douglas S. Piasecki

Inventor： Ka Y. Leung ,  Douglas S. Piasecki

IPC: H03M112

CPC classification number: H03M1/129 ,  H03M1/46

Abstract: An analog-to-digital converter configurable for converting both differential and single-ended analog signals. Charge sharing between two input capacitors and a DAC capacitor allow the full dynamic range of the ADC device to be used when full scale differential analog input signals are converted. When configured for single-ended operation, charge sharing of the half scale single-ended input analog voltage occurs between one input capacitor and the DAC capacitor to allow the full dynamic range of the ADC device to again be utilized.

Abstract translation: 可配置用于转换差分和单端模拟信号的模数转换器。 两个输入电容和DAC电容之间的电荷共享允许在转换满量程差分模拟输入信号时使用ADC器件的全部动态范围。 当配置为单端操作时，半标准单端输入模拟电压的电荷共享发生在一个输入电容和DAC电容之间，以允许再次使用ADC器件的完整动态范围。

公开(公告)号：US06404375B1

公开(公告)日：2002-06-11

申请号：US09393091

申请日：1999-09-09

Applicant: Carlos Esteban Muñoz ,  Karl Ernesto Thompson ,  Douglas S. Piasecki ,  Wai Laing Lee ,  Eric Swanson

Inventor： Carlos Esteban Muñoz ,  Karl Ernesto Thompson ,  Douglas S. Piasecki ,  Wai Laing Lee ,  Eric Swanson

IPC: H03M112

CPC classification number: H03M1/1042 ,  H03M1/0692 ,  H03M1/109 ,  H03M1/46

Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.

Abstract translation: 用于模数转换器系统的数字校准系统包括计算系统，其接收来自模数转换器的数字位，其响应于模拟输入来表示选择数模转换器的元件。 计算引擎在转换操作期间产生代表模拟输入的数字输出，以及用于在校准期间调节可调模拟源的数字值。 此外，数字系统包括二进制以下的不可配置的数模转换器，连接到转换器的比较器系统以及被配置用于SAR校准和转换的计算系统。

公开(公告)号：US5172115A

公开(公告)日：1992-12-15

申请号：US717981

申请日：1991-06-21

Applicant: Donald A. Kerth ,  Douglas S. Piasecki

Inventor： Donald A. Kerth ,  Douglas S. Piasecki

IPC: H03M1/10 ,  G01D3/00 ,  H03M1/06 ,  H03M1/12 ,  H03M3/00 ,  H03M3/02

CPC classification number: H03M1/0621 ,  G01D3/00 ,  H03M3/324 ,  H03M1/1019 ,  H03M1/12 ,  H03M3/382 ,  H03M3/458

Abstract: A ratiometric converter is provided that is comprised of a dual converter system utilizing a first converter (36) and a second converter (38). The second converter (38) is operable to receive the input voltage from a load cell (10) on sense lines (12) and (14) and compare them with an internal reference. Similarly, the first A/D converter (36) is operable to receive the reference voltage to the load cell (10) and compare it with the internal reference. The output of each of the converters (36) and (38) is then input to subtraction circuits (78) and (84), respectively, in the digital domain. In a calibration mode, switches (72) and (73) shorts the reference nodes in the load cell (10) together to determine the non-ratiometric offsets., These offsets are then stored in registers (80) and (86) for the reference voltage and the input voltage, respectively. During operation, the offsets are then input to the subtraction blocks (78) and 84) and a digital subtraction performed on the output of both converters (36) and (38). The output of the subtraction blocks (78) and (84) are then input to a ratiometric operator block (52) to perform a digital division thereon. This results in a ratiometric output that has the non-ratiometric offsets removed. Thereafter, the signal is input to a system calibration block (32) to remove ratiometric errors.

Abstract translation: 提供了一种比例转换器，其包括利用第一转换器（36）和第二转换器（38）的双转换器系统。 第二转换器（38）可操作以从感测线路（12）和（14）上的测力传感器（10）接收输入电压，并将其与内部参考值进行比较。 类似地，第一A / D转换器（36）可操作以将负载传感器（10）的参考电压接收并与内部参考值进行比较。 然后，转换器（36）和（38）中的每一个的输出分别输入到数字域中的减法电路（78）和（84）。 在校准模式中，开关（72）和（73）将测力传感器（10）中的参考节点一起缩短以确定非比例偏移量，然后将这些偏移量存储在寄存器（80）和（86）中，用于 参考电压和输入电压。 在操作期间，偏移量被输入到减法块（78）和84），并且对两个转换器（36）和（38）的输出进行数字减法。 然后将减法块（78）和（84）的输出输入到比例计算器程序块（52）以对其进行数字分频。 这导致具有非比例偏移量的比例输出。 此后，该信号被输入到系统校准块（32）以消除比例误差。

公开(公告)号：US4945262A

公开(公告)日：1990-07-31

申请号：US301926

申请日：1989-01-26

Applicant: Douglas S. Piasecki

Inventor： Douglas S. Piasecki

IPC: H03K3/3565 ,  H03K5/00 ,  H03K5/13 ,  H03K19/003

CPC classification number: H03K19/00384 ,  H03K3/3565 ,  H03K5/133 ,  H03K2005/0013 ,  H03K2005/00195

Abstract: A voltage limiter includes a first FET of a given polarity having the source electrode adapted to be connected to a positive supply terminal. There is a second FET of an opposite polarity to said first and having the source electrode adapted to be connected to a supply terminal which is negative with respect to said positive terminal. The voltage at each terminal may typically vary during operation. There is a voltage clamp means connected between the drain electrodes of said first and second FETs with the gate electrode of the first FET connected to the drain electrode of the second FET and with the gate electrode of the second FET connected to the drain electrode of the first FET, to cause the voltage across said voltage clamping means to remain constant in spite of variations in said positive and negative supplies. The voltage across the drain electrodes of the FETs is further employed as a biasing source for additional logic circuits. An output logic inverter operating with the logic circuits always has its switch point accurately defined with respect to the voltage limiting apparatus. Due to the constant voltage difference provided by the voltage limiter, the propagation delay through the logic circuits is constant with the output inverter having a controlled switching point.

Abstract translation: 电压限制器包括具有给定极性的第一FET，源极电极适于连接到正电源端子。 存在与所述第一FET相反极性的第二FET，并且源极适于连接到相对于所述正极端子的负极的供电端子。 每个终端处的电压通常可在操作期间变化。 连接在所述第一和第二FET的漏电极之间的电压钳位装置，其中第一FET的栅电极连接到第二FET的漏电极，第二FET的栅电极连接到第二FET的漏电极 第一FET，以使所述电压钳位装置两端的电压保持恒定，尽管所述正电源和负电源的变化。 进一步使用FET的漏电极两端的电压作为附加逻辑电路的偏置源。 与逻辑电路一起工作的输出逻辑逆变器总是将其切换点相对于电压限制装置精确地定义。 由于由限压器提供的恒定电压差，通过逻辑电路的传播延迟是恒定的，输出反相器具有受控的切换点。

公开(公告)号：USH497H

公开(公告)日：1988-07-05

申请号：US3170

申请日：1987-01-14

Applicant: Douglas S. Piasecki

Inventor： Douglas S. Piasecki

IPC: H03K17/22

CPC classification number: H03K17/223

Abstract: A ratioed power on reset apparatus utilizing two pairs of field effect transistors as voltage dividers to generate a power on reset signal which tracks the waveshape of an applied power signal with a slot rise time.

公开(公告)号：US08402823B2

公开(公告)日：2013-03-26

申请号：US13077098

申请日：2011-03-31

Applicant: Marty Lynn Pflum ,  Michael L. Duffy ,  Douglas S. Piasecki ,  Michael Keith Odland

Inventor： Marty Lynn Pflum ,  Michael L. Duffy ,  Douglas S. Piasecki ,  Michael Keith Odland

IPC: G01M1/00

CPC classification number: G01F15/063 ,  G01D4/02 ,  G01R11/16 ,  H03K3/356121

Abstract: A metering system can include a pull up circuit to be selectively coupled between a voltage node and a metering line that communicates a signal indicative of status of a flow line through which a metered substance flows. An impedance of the pull up circuit is set to reduce power consumption based on a calibration, and the pull up circuit can be disabled between sampling of the signal to reduce power consumption.

Abstract translation: 计量系统可以包括上拉电路，其被选择性地耦合在电压节点和计量线之间，所述电压节点和计量线传达指示计量物质流过的流动线状态的信号。 上拉电路的阻抗被设置为基于校准来降低功耗，并且可以在采样信号之间禁止上拉电路以降低功耗。