公开(公告)号：US06456220B1

公开(公告)日：2002-09-24

申请号：US09595959

申请日：2000-06-19

Applicant: Ka Y. Leung ,  Douglas S. Piasecki

Inventor： Ka Y. Leung ,  Douglas S. Piasecki

IPC: H03M112

CPC classification number: H03M1/129 ,  H03M1/46

Abstract: An analog-to-digital converter configurable for converting both differential and single-ended analog signals. Charge sharing between two input capacitors and a DAC capacitor allow the full dynamic range of the ADC device to be used when full scale differential analog input signals are converted. When configured for single-ended operation, charge sharing of the half scale single-ended input analog voltage occurs between one input capacitor and the DAC capacitor to allow the full dynamic range of the ADC device to again be utilized.

Abstract translation: 可配置用于转换差分和单端模拟信号的模数转换器。 两个输入电容和DAC电容之间的电荷共享允许在转换满量程差分模拟输入信号时使用ADC器件的全部动态范围。 当配置为单端操作时，半标准单端输入模拟电压的电荷共享发生在一个输入电容和DAC电容之间，以允许再次使用ADC器件的完整动态范围。

公开(公告)号：US06404375B1

公开(公告)日：2002-06-11

申请号：US09393091

申请日：1999-09-09

Applicant: Carlos Esteban Muñoz ,  Karl Ernesto Thompson ,  Douglas S. Piasecki ,  Wai Laing Lee ,  Eric Swanson

Inventor： Carlos Esteban Muñoz ,  Karl Ernesto Thompson ,  Douglas S. Piasecki ,  Wai Laing Lee ,  Eric Swanson

IPC: H03M112

CPC classification number: H03M1/1042 ,  H03M1/0692 ,  H03M1/109 ,  H03M1/46

Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.

Abstract translation: 用于模数转换器系统的数字校准系统包括计算系统，其接收来自模数转换器的数字位，其响应于模拟输入来表示选择数模转换器的元件。 计算引擎在转换操作期间产生代表模拟输入的数字输出，以及用于在校准期间调节可调模拟源的数字值。 此外，数字系统包括二进制以下的不可配置的数模转换器，连接到转换器的比较器系统以及被配置用于SAR校准和转换的计算系统。

公开(公告)号：US5172115A

公开(公告)日：1992-12-15

申请号：US717981

申请日：1991-06-21

Applicant: Donald A. Kerth ,  Douglas S. Piasecki

Inventor： Donald A. Kerth ,  Douglas S. Piasecki

IPC: H03M1/10 ,  G01D3/00 ,  H03M1/06 ,  H03M1/12 ,  H03M3/00 ,  H03M3/02

CPC classification number: H03M1/0621 ,  G01D3/00 ,  H03M3/324 ,  H03M1/1019 ,  H03M1/12 ,  H03M3/382 ,  H03M3/458

Abstract: A ratiometric converter is provided that is comprised of a dual converter system utilizing a first converter (36) and a second converter (38). The second converter (38) is operable to receive the input voltage from a load cell (10) on sense lines (12) and (14) and compare them with an internal reference. Similarly, the first A/D converter (36) is operable to receive the reference voltage to the load cell (10) and compare it with the internal reference. The output of each of the converters (36) and (38) is then input to subtraction circuits (78) and (84), respectively, in the digital domain. In a calibration mode, switches (72) and (73) shorts the reference nodes in the load cell (10) together to determine the non-ratiometric offsets., These offsets are then stored in registers (80) and (86) for the reference voltage and the input voltage, respectively. During operation, the offsets are then input to the subtraction blocks (78) and 84) and a digital subtraction performed on the output of both converters (36) and (38). The output of the subtraction blocks (78) and (84) are then input to a ratiometric operator block (52) to perform a digital division thereon. This results in a ratiometric output that has the non-ratiometric offsets removed. Thereafter, the signal is input to a system calibration block (32) to remove ratiometric errors.

Abstract translation: 提供了一种比例转换器，其包括利用第一转换器（36）和第二转换器（38）的双转换器系统。 第二转换器（38）可操作以从感测线路（12）和（14）上的测力传感器（10）接收输入电压，并将其与内部参考值进行比较。 类似地，第一A / D转换器（36）可操作以将负载传感器（10）的参考电压接收并与内部参考值进行比较。 然后，转换器（36）和（38）中的每一个的输出分别输入到数字域中的减法电路（78）和（84）。 在校准模式中，开关（72）和（73）将测力传感器（10）中的参考节点一起缩短以确定非比例偏移量，然后将这些偏移量存储在寄存器（80）和（86）中，用于 参考电压和输入电压。 在操作期间，偏移量被输入到减法块（78）和84），并且对两个转换器（36）和（38）的输出进行数字减法。 然后将减法块（78）和（84）的输出输入到比例计算器程序块（52）以对其进行数字分频。 这导致具有非比例偏移量的比例输出。 此后，该信号被输入到系统校准块（32）以消除比例误差。

公开(公告)号：US4945262A

公开(公告)日：1990-07-31

申请号：US301926

申请日：1989-01-26

Applicant: Douglas S. Piasecki

Inventor： Douglas S. Piasecki

IPC: H03K3/3565 ,  H03K5/00 ,  H03K5/13 ,  H03K19/003

CPC classification number: H03K19/00384 ,  H03K3/3565 ,  H03K5/133 ,  H03K2005/0013 ,  H03K2005/00195

Abstract: A voltage limiter includes a first FET of a given polarity having the source electrode adapted to be connected to a positive supply terminal. There is a second FET of an opposite polarity to said first and having the source electrode adapted to be connected to a supply terminal which is negative with respect to said positive terminal. The voltage at each terminal may typically vary during operation. There is a voltage clamp means connected between the drain electrodes of said first and second FETs with the gate electrode of the first FET connected to the drain electrode of the second FET and with the gate electrode of the second FET connected to the drain electrode of the first FET, to cause the voltage across said voltage clamping means to remain constant in spite of variations in said positive and negative supplies. The voltage across the drain electrodes of the FETs is further employed as a biasing source for additional logic circuits. An output logic inverter operating with the logic circuits always has its switch point accurately defined with respect to the voltage limiting apparatus. Due to the constant voltage difference provided by the voltage limiter, the propagation delay through the logic circuits is constant with the output inverter having a controlled switching point.

Abstract translation: 电压限制器包括具有给定极性的第一FET，源极电极适于连接到正电源端子。 存在与所述第一FET相反极性的第二FET，并且源极适于连接到相对于所述正极端子的负极的供电端子。 每个终端处的电压通常可在操作期间变化。 连接在所述第一和第二FET的漏电极之间的电压钳位装置，其中第一FET的栅电极连接到第二FET的漏电极，第二FET的栅电极连接到第二FET的漏电极 第一FET，以使所述电压钳位装置两端的电压保持恒定，尽管所述正电源和负电源的变化。 进一步使用FET的漏电极两端的电压作为附加逻辑电路的偏置源。 与逻辑电路一起工作的输出逻辑逆变器总是将其切换点相对于电压限制装置精确地定义。 由于由限压器提供的恒定电压差，通过逻辑电路的传播延迟是恒定的，输出反相器具有受控的切换点。

公开(公告)号：USH497H

公开(公告)日：1988-07-05

申请号：US3170

申请日：1987-01-14

Applicant: Douglas S. Piasecki

Inventor： Douglas S. Piasecki

IPC: H03K17/22

CPC classification number: H03K17/223

Abstract: A ratioed power on reset apparatus utilizing two pairs of field effect transistors as voltage dividers to generate a power on reset signal which tracks the waveshape of an applied power signal with a slot rise time.

公开(公告)号：US08633844B2

公开(公告)日：2014-01-21

申请号：US13362450

申请日：2012-01-31

Applicant: Douglas S. Piasecki

Inventor： Douglas S. Piasecki

IPC: H03M1/12

CPC classification number: H03M1/468

Abstract: In one embodiment, a data acquisition circuit includes an analog multiplexer to receive analog signals and select an analog signal for output, an ADC coupled to the multiplexer to receive the analog signal and perform a conversion of the analog signal to a N-bit digital value in at least N clock cycles, and a controller coupled to the ADC to enable the ADC to compare the analog signal to a second analog signal in a single clock cycle.

Abstract translation: 在一个实施例中，数据采集电路包括模拟多路复用器，用于接收模拟信号并选择模拟信号进行输出，ADC耦合到多路复用器以接收模拟信号并执行模拟信号转换为N位数字值 在至少N个时钟周期中，以及耦合到ADC的控制器，使ADC能够在单个时钟周期内将模拟信号与第二模拟信号进行比较。

公开(公告)号：US07852061B2

公开(公告)日：2010-12-14

申请号：US11865648

申请日：2007-10-01

Applicant: Jia-Hau Liu ,  Alan L. Westwick ,  Douglas S. Piasecki

Inventor： Jia-Hau Liu ,  Alan L. Westwick ,  Douglas S. Piasecki

IPC: G05F3/16

CPC classification number: G05F3/30 ,  H02M2001/0032 ,  Y02B70/16 ,  Y10S323/907

Abstract: An apparatus comprises a band gap voltage generator circuit for generating a band gap voltage. A temperature invariant current generator is located within the band gap voltage generator circuit for generating a temperature invariant current. A temperature invariant current correction circuit is located within the band gap voltage generator circuit and adjusts the output voltage responsive to the temperature invariant current without altering temperature characteristics of the temperature invariant current.

Abstract translation: 一种装置包括用于产生带隙电压的带隙电压发生器电路。 温度不变电流发生器位于带隙电压发生器电路内，用于产生温度不变电流。 温度不变电流校正电路位于带隙电压发生器电路内，并根据温度不变电流调节输出电压，而不改变温度不变电流的温度特性。

公开(公告)号：US07660968B2

公开(公告)日：2010-02-09

申请号：US11772184

申请日：2007-06-30

Applicant: Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alan Storvik ,  Paul Highley ,  Douglas R. Holberg

Inventor： Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alan Storvik ,  Paul Highley ,  Douglas R. Holberg

IPC: G06F13/00

CPC classification number: G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks. A reconfigurable interface selectively interfaces between the other of the input or output of the functional blocks and a select one or ones of the plurality of input/output pins, such that the processor core can be interfaced with the select one or ones of the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the select ones of the plurality of functional blocks and the associated functionality in accordance with configuration information. A non-volatile memory is provided for storing information for use in association with the configuration information, such that the stored information can be altered.

Abstract translation: 可重构处理器包括用于在一组指令上操作以执行预定义的处理的处理器核心，并且除了多个功能输入/输出块之外还包括多个输入/输出引脚。 这些功能块允许处理核与多个输入/输出引脚相连接，每个功能输入/输出块具有相关联的和预定的功能。 该功能包括作为输入的功能的输出，功能定义的功能。 每个功能输入/输出块对多个输入/输出引脚的定义数量要求，其中所有多个功能输入/输出块中的所有定义数目的总数超过多个输入/ 输出引脚，并且其中处理器核心与每个功能块的输入或输出中的一个接口。 可重配置接口选择性地在功能块的输入或输出中的另一个与多个输入/输出引脚中的选择一个或多个输入/输出引脚之间进行接口，使得处理器核可以与选择的一个或多个输入/ 输出引脚。 可重配置接口可操作以根据配置信息定义多个输入/输出引脚中的每一个如何与多个功能块中的选择功能块和相关联的功能接口。 提供非易失性存储器用于存储与配置信息相关联使用的信息，使得可以改变所存储的信息。

公开(公告)号：US07171542B1

公开(公告)日：2007-01-30

申请号：US09885459

申请日：2001-06-19

Applicant: Donald E. Alfano ,  Danny Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y Leung ,  Brian Caloway ,  Alvin Storvik ,  Paul Highley ,  Douglas R Holberg

Inventor： Donald E. Alfano ,  Danny Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y Leung ,  Brian Caloway ,  Alvin Storvik ,  Paul Highley ,  Douglas R Holberg

IPC: G06F13/00

CPC classification number: G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins through select ones of a plurality of functional blocks. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core an the functionality associated therewith. The functional blocks provide the interface of the processor core with the input/output pins.

Abstract translation: 集成电路中的可重构处理器系统包括对一组指令进行操作以执行预定义的处理的处理器核心。 提供多个输入/输出引脚用于与外部信号进行接口。 可重新配置的接口通过多个功能块中的选择的接口在处理器核心和输入/输出引脚之间进行接口。 可重构接口可操作以定义多个输入/输出引脚中的每一个如何与处理器核心与处理器核心相连接的功能。 功能块提供处理器内核与输入/输出引脚的接口。

公开(公告)号：US06313779B1

公开(公告)日：2001-11-06

申请号：US09637493

申请日：2000-08-11

Applicant: Ka Y. Leung ,  Douglas S. Piasecki

Inventor： Ka Y. Leung ,  Douglas S. Piasecki

IPC: H03M112

CPC classification number: H03M1/129 ,  H03M1/46

Abstract: An analog-to-digital converter amplifier that is configurable with one gain for driving one terminal of a sampling capacitor while the other terminal is sampled to an analog input signal during one time period, and configurable with a different gain for comparing the analog sample with a DAC-generated reference voltage during a second time period.

Abstract translation: 模数转换器放大器可配置一个增益，用于驱动采样电容器的一个端子，而另一个端子在一个时间段内被采样到模拟输入信号，并可配置不同的增益，用于将模拟采样与 在第二时间段期间DAC产生的参考电压。