公开(公告)号：US20140264242A1

公开(公告)日：2014-09-18

申请号：US14109415

申请日：2013-12-17

申请人： Crossbar, Inc.

发明人： Scott Brad HERNER ,  Hagop NAZARIAN

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2463 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1675

摘要： A disturb-resistant nonvolatile memory device includes a substrate, a dielectric material overlying the semiconductor substrate, a first cell comprising a first wiring structure extending in a first direction overlying the dielectric material, a first contact region, a first resistive switching media, and a second wiring structure extending in a second direction orthogonal to the first direction, a second cell comprising the first wiring structure, a second contact region, a second resistive switching media, and a third wiring structure separated from the second wiring structure and parallel to the second wiring structure, and a dielectric material disposed at least in a region between the first switching region and the second switching region to electrically and physically isolate the first switching region and the second switching region.

摘要翻译： 耐干扰非易失性存储器件包括衬底，覆盖在半导体衬底上的电介质材料，第一电池包括在覆盖电介质材料的第一方向上延伸的第一布线结构，第一接触区，第一电阻开关介质和 第二布线结构，沿与第一方向正交的第二方向延伸;第二单元，包括第一布线结构，第二接触区，第二电阻切换介质和与第二布线结构分离并平行于第二布线结构的第三布线结构 布线结构和至少设置在第一开关区域和第二开关区域之间的区域中的电介质材料，以电和物理地隔离第一开关区域和第二开关区域。

公开(公告)号：US20130234092A1

公开(公告)日：2013-09-12

申请号：US13862353

申请日：2013-04-12

申请人： CROSSBAR, INC.

发明人： Harry GEE ,  Sung Hyun JO ,  Hagop NAZARIAN ,  Scott Brad HERNER

IPC分类号： H01L45/00

CPC分类号： H01L45/1683 ,  G11C13/0007 ,  G11C2213/71 ,  H01L21/4763 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/148 ,  H01L45/16

摘要： A method of forming a non-volatile memory device. A substrate is provided and a first dielectric material forms overlying the substrate. A first polysilicon material is deposited overlying the first dielectric material. A second dielectric material is deposited overlying the first polysilicon material. A second polysilicon material is deposited overlying the second dielectric material. A third dielectric material is formed overlying the second polysilicon material. The third dielectric material, the second polysilicon material, the second dielectric material, and the first polysilicon material is subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material, a third wordline and associated with a third switching device, and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and overlies the amorphous silicon material and connected to a common bitline.

摘要翻译： 一种形成非易失性存储器件的方法。 提供衬底并且形成覆盖衬底的第一介电材料。 第一多晶硅材料沉积在第一介电材料上。 沉积在第一多晶硅材料上的第二介电材料。 第二多晶硅材料沉积在第二介电材料上。 形成覆盖第二多晶硅材料的第三介电材料。 对第三介电材料，第二多晶硅材料，第二介电材料和第一多晶硅材料进行第一图案和蚀刻工艺以形成与第一开关器件相关联的第一字线和与第二开关器件相关联的第二字线 来自第一多晶硅材料的第三字线和与第三开关器件相关联的第三字线以及与第四开关器件相关联的第四字线从第二多晶硅材料。 形成通孔开口以将第一字线与第二字线分开，并将第三字线与第四字线分开。 将非晶硅开关材料顺应地沉积在通孔开口上方。 金属材料填充通孔开口并覆盖非晶硅材料并连接到公共位线。

公开(公告)号：US20150228334A1

公开(公告)日：2015-08-13

申请号：US14692677

申请日：2015-04-21

申请人： Crossbar, Inc.

发明人： Hagop NAZARIAN ,  Sung Hyun JO ,  Wei LU

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C8/14 ,  G11C11/1653 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/15 ,  G11C2213/33 ,  G11C2213/56 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148

摘要： A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.

摘要翻译： 非易失性存储器件包括沿着第一方向延伸的字线; 沿第二方向延伸的位线; 具有耦合到位线的读取晶体管，至少一个两端存储单元和选择晶体管的存储单元，所述双端存储单元具有耦合到字线的第一端和耦合到栅极的第二端 的读取晶体管。 两端存储单元的第二端耦合到由选择晶体管的漏极和读取晶体管的栅极共享的公共节点。

公开(公告)号：US20140327470A1

公开(公告)日：2014-11-06

申请号：US14335507

申请日：2014-07-18

申请人： Crossbar, Inc.

发明人： Hagop NAZARIAN ,  Sang Thanh NGUYEN ,  Tanmay KUMAR

IPC分类号： H03K19/177 ,  H01L21/8234 ,  H03K19/00

CPC分类号： H03K19/17764 ,  H01L21/823437 ,  H03K19/0013 ,  H03K19/0944 ,  H03K19/17728 ,  H03K19/1776 ,  H03K19/17776

摘要： A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, applying a first programming voltage to a shared node of a second electrode of the first resistive element, a first electrode of the second resistive element, and to a gate of a transistor element, and changing a resistance state of the first resistive element to a low resistance state while maintaining a resistance state of the second resistive element, when a voltage difference between the first programming voltage at the second terminal and the first input voltage at the first terminal exceeds a programming voltage associated with the first resistive element.

摘要翻译： 一种FPGA的方法包括将第一电阻元件的第一电极耦合到第一输入电压，将第二电阻元件的第二电极耦合到第二输入电压，将第一编程电压施加到第二电极的第二电极的共享节点 所述第一电阻元件，所述第二电阻元件的第一电极和晶体管元件的栅极，并且在保持所述第二电阻元件的电阻状态的同时将所述第一电阻元件的电阻状态改变为低电阻状态， 第二端子处的第一编程电压与第一端子处的第一输入电压之间的电压差超过与第一电阻元件相关联的编程电压。

公开(公告)号：US20140268997A1

公开(公告)日：2014-09-18

申请号：US13954853

申请日：2013-07-30

申请人： Crossbar, Inc.

发明人： Hagop NAZARIAN ,  Sang NGUYEN

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0002 ,  G11C13/0028 ,  G11C13/003 ,  G11C2213/77 ,  G11C2213/78 ,  G11C2213/79

摘要： Providing for programming a two-terminal memory cell array with low sneak path current is described herein. Groups of two-terminal memory cells can be arranged into blocks or sub-blocks, along sets of bitlines and local wordlines. Further, groups of local wordlines within a given sub-block can be electrically isolated from bitlines outside the sub-block. A programming signal can be applied to the two-terminal memory cells from an associated local wordline thereof. Sneak path currents can be mitigated or avoided with respect to bitlines outside a particular sub-block, or on non-selected wordlines of the sub-block. This can significantly reduce a magnitude of combined sneak path current within the sub-block in response to the programming operation.

摘要翻译： 本文描述了提供用于编程具有低潜行路径电流的双端存储单元阵列。 两组存储器单元组可以沿着位线和本地字线排列成块或子块。 此外，给定子块内的本地字线组可以与子块之外的位线电隔离。 编程信号可以从相关联的本地字线应用于两端存储器单元。 相对于特定子块之外的位线或子块的未选择的字线，可以减轻或避免潜行路径电流。 这可以响应于编程操作而显着地减小子块内组合的潜行路径电流的大小。

公开(公告)号：US20150248931A1

公开(公告)日：2015-09-03

申请号：US14194402

申请日：2014-02-28

申请人： Crossbar, Inc.

发明人： Hagop NAZARIAN

IPC分类号： G11C13/00 ,  H01L27/24

CPC分类号： G11C13/004 ,  G11C11/1659 ,  G11C11/56 ,  G11C11/5607 ,  G11C11/5614 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0014 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/75 ,  H01L27/2436 ,  H01L27/2463

摘要： Providing for a high performance and efficiency NAND architecture is described herein. By way of example, a NAND array is disclosed comprising memory cells having a 1 transistor-1 two-terminal memory device (IT-1D) arrangement. Memory cells of the NAND array can be arranged electrically in serial with respect to each other, from source to drain. Moreover, respective memory cells comprise a transistor component connected in parallel to a two-terminal memory device. In some embodiments, a resistance of the activated transistor component is selected to be substantially less than that of the two-terminal memory device, and the resistance of the deactivated transistor component is selected to be substantially higher than the two-terminal memory device. Accordingly, by activating or deactivating the transistor component, a signal applied to the memory cell can be shorted past the two-terminal memory device, or directed through the two-terminal memory device, respectively.

摘要翻译： 本文描述了提供高性能和高效率的NAND架构。 作为示例，公开了包括具有1晶体管1两端存储器件（IT-1D）布置的存储器单元的NAND阵列。 NAND阵列的存储单元可以相对于彼此串联地从源极到漏极布置。 此外，各个存储单元包括并联连接到两端存储器件的晶体管组件。 在一些实施例中，激活的晶体管部件的电阻被选择为基本上小于两端存储器件的电阻，并且去激活的晶体管部件的电阻被选择为显着高于两端存储器件。 因此，通过激活或去激活晶体管组件，施加到存储单元的信号可以分别通过两端存储器件短路，或通过两端存储器件引导。

公开(公告)号：US20140320166A1

公开(公告)日：2014-10-30

申请号：US14166700

申请日：2014-01-28

申请人： Crossbar, Inc.

发明人： Hagop NAZARIAN ,  Sang Thanh NGUYEN ,  Tanmay KUMAR

IPC分类号： H03K19/00 ,  H03K19/177 ,  H03K19/0944

CPC分类号： H03K19/0013 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0069 ,  H03K19/0944 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17776

摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

公开(公告)号：US20130214241A1

公开(公告)日：2013-08-22

申请号：US13733828

申请日：2013-01-03

申请人： Crossbar, Inc.

发明人： Scott Brad HERNER ,  Hagop NAZARIAN

IPC分类号： H01L27/24

CPC分类号： H01L27/2463 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1675

摘要： A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction. The first strip of switching material, the second strip of switching material, the contact material, and the first wiring material are subjected to a second patterning and etching process to form at least a first switching element from the first strip of switching material and at least a second switching element from the second strip of switching material, and a first wiring structure comprising at least the first wiring material and the contact material. The first wiring structure being is in a second direction at an angle to the first direction.

摘要翻译： 一种形成抗干扰非易失性存储器件的方法。 该方法包括提供具有表面区域并形成覆盖表面区域的第一电介质材料的半导体衬底。 第一布线材料覆盖在第一介电材料上，掺杂多晶硅材料覆盖在第一布线材料上，非晶硅开关材料覆盖在所述多晶硅材料上。 对开关材料进行第一图案化和蚀刻工艺，以将第一条开关材料与在第一方向上空间取向的第二开关条分离。 第一切换材料条，第二条切换材料，接触材料和第一布线材料经受第二图案化和蚀刻工艺，以从第一条开关材料形成至少第一开关元件，并且至少 来自所述第二开关材料条的第二开关元件，以及至少包括所述第一布线材料和所述接触材料的第一布线结构。 第一布线结构处于与第一方向成一定角度的第二方向。

公开(公告)号：US20150188051A1

公开(公告)日：2015-07-02

申请号：US14643832

申请日：2015-03-10

申请人： Crossbar, Inc.

发明人： Harry GEE ,  Sung Hyun JO ,  Hagop NAZARIAN ,  Scott Brad HERNER

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1683 ,  G11C13/0007 ,  G11C2213/71 ,  H01L21/4763 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/148 ,  H01L45/16

摘要： A method of forming a non-volatile memory device. The method forms a vertical stack of first polysilicon material and a second polysilicon material layer isolated by a dielectric material. The polysilicon material layers and the dielectric material are subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material layer, and a third wordline associated with a third switching device and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and connects to a common bitline.

摘要翻译： 一种形成非易失性存储器件的方法。 该方法形成由电介质材料隔离的第一多晶硅材料和第二多晶硅材料层的垂直堆叠。 对多晶硅材料层和电介质材料进行第一图案和蚀刻处理，以形成与第一开关器件相关联的第一字线和与第一多晶硅材料层相关联的第二开关器件的第二字线，以及与第一字线相关联的第三字线 第三开关器件和与第四开关器件相关的第四字线与第二多晶硅材料相连。 形成通孔开口以将第一字线与第二字线分开，并将第三字线与第四字线分开。 将非晶硅开关材料顺应地沉积在通孔开口上方。 金属材料填充通孔开口并连接到通用位线。

公开(公告)号：US20140292368A1

公开(公告)日：2014-10-02

申请号：US14304572

申请日：2014-06-13

申请人： Crossbar, Inc.

发明人： Hagop NAZARIAN ,  Sang Thanh NGUYEN ,  Tanmay KUMAR

IPC分类号： H03K19/177 ,  H03K19/003 ,  G11C13/00 ,  H03K19/0944 ,  H03K19/00

CPC分类号： H03K19/17776 ,  G11C13/0021 ,  H01L27/101 ,  H03K19/0013 ,  H03K19/00315 ,  H03K19/0944 ,  H03K19/1776

摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

摘要翻译： 本文描述了利用电阻随机存取存储器（RRAM）技术提供现场可编程门阵列（FPGA）。 作为示例，FPGA可以包括具有由垂直信号输出线交叉的并行信号输入线的开关块互连。 可以在信号输入线和信号输出线的各个交叉处形成RRAM存储器单元。 RRAM存储器单元可以包括分压器，该分压器包括跨FPGA的VCC和VSS串联电串联的多个可编程电阻元件。 分压器的公共节点驱动配置为激活或去激活交叉的通路晶体管的栅极。 所公开的RRAM存储器可以提供高晶体管密度，高逻辑利用率，快速的编程速度，辐射抗扰度，快速上电和对FPGA技术的显着益处。