发明申请
US20150228334A1 MEMORY ARRAY ARCHITECTURE WITH TWO-TERMINAL MEMORY CELLS 有权
具有两个终端记忆细胞的记忆阵列结构

  • 专利标题: MEMORY ARRAY ARCHITECTURE WITH TWO-TERMINAL MEMORY CELLS
  • 专利标题(中): 具有两个终端记忆细胞的记忆阵列结构
  • 申请号: US14692677
    申请日: 2015-04-21
  • 公开(公告)号: US20150228334A1
    公开(公告)日: 2015-08-13
  • 发明人: Hagop NAZARIANSung Hyun JOWei LU
  • 申请人: Crossbar, Inc.
  • 主分类号: G11C13/00
  • IPC分类号: G11C13/00
MEMORY ARRAY ARCHITECTURE WITH TWO-TERMINAL MEMORY CELLS
摘要:
A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.
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