发明申请
- 专利标题: MEMORY ARRAY ARCHITECTURE WITH TWO-TERMINAL MEMORY CELLS
- 专利标题(中): 具有两个终端记忆细胞的记忆阵列结构
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申请号: US14692677申请日: 2015-04-21
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公开(公告)号: US20150228334A1公开(公告)日: 2015-08-13
- 发明人: Hagop NAZARIAN , Sung Hyun JO , Wei LU
- 申请人: Crossbar, Inc.
- 主分类号: G11C13/00
- IPC分类号: G11C13/00
摘要:
A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.
公开/授权文献
- US09620206B2 Memory array architecture with two-terminal memory cells 公开/授权日:2017-04-11
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