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1.发明授权
公开(公告)号：US4081794A
公开(公告)日：1978-03-28
申请号：US673080
申请日：1976-04-02
CPC分类号： H01L27/1021 , G11C11/23 , G11C11/34 , G11C17/06 , G11C17/14 , Y10S257/917
摘要： A memory plane for an archival, non-volatile mass storage memory has a planar semiconductor diode with each of a plurality of small P-N junction diodes alloyed into the surface of its fabricated layer responsive to a selectively-actuated scanned energy beam at each location corresponding to a first binary value in a planar array of data sites. Formation of a P-N junction is prevented at each of the remaining sites of the planar data array to provide storage of data having the remaining binary value.Several alternative methods for formation of the alloy junction surface diodes are disclosed.
摘要翻译： 用于归档非挥发性大容量存储器的存储器平面具有平面半导体二极管，其中多个小PN结二极管中的每一个合成到其制造的层的表面中，其响应于对应于每个位置处的每个位置处的选择性致动的扫描能量束 数据站点的平面数组中的第一个二进制值。 在平面数据阵列的每个剩余位置处防止形成P-N结以提供具有剩余二进制值的数据的存储。
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2.发明授权
公开(公告)号：US4130891A
公开(公告)日：1978-12-19
申请号：US822429
申请日：1977-08-08
IPC分类号： G11C17/06 , H01L21/265 , G11C11/40
CPC分类号： H01L21/26506 , G11C17/06 , H01L21/26513
摘要： One of a multiplicity of data values is permanently recorded at each data site in a two-dimensional data site array defined upon the surface of a semiconductor diode target by implanting an auxiliary bit thereat having an associated one of a multiplicity of possible dopant concentrations, at a uniform implantation depth, or of different implantation depths, at a uniform doping concentration, into a fabricated layer of the diode, responsive to respectively controlling the fluence or the landing energy of a writing ion beam.
摘要翻译： 在多个数据值中的一个数据值被永久地记录在二维数据站点阵列中的每个数据站点上，该二维数据站点阵列在半导体二极管靶的表面上通过在其上注入具有多个可能的掺杂剂浓度的相关联的一个辅助位， 均匀的注入深度或不同的注入深度以均匀的掺杂浓度转换成二极管的制造层，响应于分别控制写入离子束的注量或着陆能量。
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3.发明授权Dual dielectric field effect transistors for protected gate structures for improved yield and performance in thin film transistor matrix addressed liquid crystal displays 失效用于保护栅极结构的双电介质场效应晶体管，用于改善薄膜晶体管矩阵寻址液晶显示器的产量和性能
公开(公告)号：US5148248A
公开(公告)日：1992-09-15
申请号：US303091
申请日：1989-01-26
IPC分类号： H01L27/12
CPC分类号： H01L27/12
摘要： A dual dielectric structure is employed in the fabrication of thin film field effect transistors in a matrix addressed liquid display to provide improved transistor device characteristics and also to provide both electricial and chemical isolation for material employed in the gate metallization layer. In particular, the use of a layer of silicon oxide over the gate metallization layer is not only consistent with providing the desired electrical and chemical isolation, but also with providing redundant gate metallization material to be employed beneath source or data lines for electrical circuit redundancy. Gate line redundancy is also possible. The electrical and chemical isolation provided by the dual dielectric layer reduces the possibilities of short circuits occurring in the display. The absence of short circuits together with the improved redundancy characteristics significantly increase manufacturing yield. As display sizes increase, the yield problem becomes more and more significant, generally growing as the square of the diagonal measurement of the screen. The structure in the present invention also significantly reduces gate leakage current. In the process and structure of the present invention, gate electrode material is separated from semiconductor material by the aforementioned dual dielectric, typically comprising layers of silicon oxide disposed beneath a layer of silicon nitride which is, in turn, disposed beneath the active amorphous silicon semiconductor material.
摘要翻译： 在矩阵寻址的液体显示器中制造薄膜场效应晶体管时采用双电介质结构以提供改进的晶体管器件特性，并且还为栅极金属化层中使用的材料提供电化学和化学隔离。 特别地，在栅极金属化层上使用一层氧化硅不仅与提供期望的电和化学隔离一致，而且还提供要用于电路冗余的源极或数据线下方的冗余栅极金属化材料。 栅线冗余也是可能的。 由双电介质层提供的电气和化学隔离减少了在显示器中发生短路的可能性。 没有短路以及改进的冗余特性显着提高了制造产量。 随着显示尺寸的增加，产量问题变得越来越重要，通常随屏幕对角线测量的平方而增长。 本发明的结构也显着地降低了栅极漏电流。 在本发明的方法和结构中，栅极电极材料通过上述双电介质与半导体材料分离，所述双电介质通常包括设置在有源非晶硅半导体下方的氮化硅层下方的氧化硅层 材料。
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公开(公告)号：US4196373A
公开(公告)日：1980-04-01
申请号：US894757
申请日：1978-04-10
申请人： Harold G. Parks
发明人： Harold G. Parks
CPC分类号： H01J29/46
摘要： Electron optics apparatus, for use in electron-beam lithography, electron-beam-addressable memory tubes and the like, utilizes a tri-potential collimating condenser lens and a multi-element matrix lens of the "flys eye" type with coarse deflection elements positioned therebetween to deflect the collimated electron beam from the condenser lens to the appropriate aperture in the matrix of lenslets. The condenser lens electrode and matrix lens electrode closest to one another, as well as the coarse deflection electrodes therebetween, are substantially the only elements in the apparatus which float at a relatively high electrical potential, thereby simplifying the requirements of peripheral circuitry while retaining the advantages of the "flys eye" matrix lens.
摘要翻译： 用于电子束光刻，电子束可寻址存储管等的电子光学装置利用三电位准直聚光透镜和“飞眼”型的多元矩阵透镜，其中定位有粗偏转元件 以将准直电子束从聚光透镜偏转到小透镜矩阵中的适当孔径。 彼此最靠近的聚光透镜电极和矩阵透镜电极以及它们之间的粗偏转电极基本上是在相对较高电势下浮动的设备中的唯一元件，从而简化了外围电路的要求，同时保持了优点 的“飞眼”矩阵镜头。
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5.发明授权Dual dielectric field effect transistors for protected gate structures for improved yield and performance in thin film transistor matrix addressed liquid crystal displays 失效用于保护栅极结构的双电介质场效应晶体管，用于改善薄膜晶体管矩阵寻址液晶显示器的产量和性能
公开(公告)号：US5210045A
公开(公告)日：1993-05-11
申请号：US862474
申请日：1992-05-18
IPC分类号： H01L27/12
CPC分类号： H01L27/12 , Y10S148/043 , Y10S438/98
摘要： A dual dielectric structure is employed in the fabrication of thin film field effect transistors in a matrix addressed liquid display to provide improved transistor device characteristics and also to provide both electrical and chemical isolation for material employed in the gate metallization layer. In particular, the use of a layer of silicon oxide over the gate metallization layer is not only consistent with providing the desired electrical and chemical isolation, but also with providing redundant gate metallization material to be employed beneath source or data lines for electrical circuit redundancy. Gate line redundancy is also possible. The electrical and chemical isolation provided by the dual dielectric layer reduces the possibilities of short circuits occurring in the display. The absence of short circuits together with the improved redundancy characteristics significantly increase manufacturing yield. As display sizes increase, the yield problem becomes more and more significant, generally growing as the square of the diagonal measurement of the screen. The structure in the present invention also significantly reduces gate leakage current. In the process and structure of the present invention, gate electrode material is separated from semiconductor material by the aforementioned dual dielectric, typically comprising layers of silicon oxide disposed beneath a layer of silicon nitride which is, in turn, disposed beneath the active amorphous silicon semiconductor material.
摘要翻译： 双电介质结构用于在矩阵寻址液体显示器中制造薄膜场效应晶体管以提供改进的晶体管器件特性，并且还为栅极金属化层中所采用的材料提供电和化学隔离。 特别地，在栅极金属化层上使用一层氧化硅不仅与提供期望的电和化学隔离一致，而且还提供要用于电路冗余的源极或数据线下方的冗余栅极金属化材料。 栅线冗余也是可能的。 由双电介质层提供的电气和化学隔离减少了在显示器中发生短路的可能性。 没有短路以及改进的冗余特性显着提高了制造产量。 随着显示尺寸的增加，产量问题变得越来越重要，通常随屏幕对角线测量的平方而增长。 本发明的结构也显着地降低了栅极漏电流。 在本发明的方法和结构中，栅极电极材料通过上述双电介质与半导体材料分离，所述双电介质通常包括设置在有源非晶硅半导体下方的氮化硅层下方的氧化硅层 材料。
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6.发明授权
公开(公告)号：US4704783A
公开(公告)日：1987-11-10
申请号：US859526
申请日：1986-05-05
IPC分类号： H01L27/12 , H01L21/312 , H01L21/336 , H01L21/56 , H01L29/78 , H01L29/786
CPC分类号： H01L21/312 , H01L21/56 , H01L29/78669 , H01L2924/0002 , Y10S438/906 , Y10S438/958
摘要： An organic or inorganic base solution is employed as a means for passivating the back channel region of an amorphous silicon FET device following plasma etching of the back channel region. The passivation provided significantly reduces back channel leakage currents resulting in FET devices which are compatible with conventional processing methods and which exhibit desirable properties for use in liquid crystal display systems.
摘要翻译： 使用有机或无机碱溶液作为在后沟道区域的等离子体蚀刻之后钝化非晶硅FET器件的背沟道区域的手段。 提供的钝化显着减少了反向沟道泄漏电流，导致与常规处理方法相容并且显示出用于液晶显示系统的期望特性的FET器件。
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公开(公告)号：US07271608B1
公开(公告)日：2007-09-18
申请号：US10716686
申请日：2003-11-19
IPC分类号： G01R31/02
CPC分类号： G01R31/2856 , G01R31/2879
摘要： A prognostic cell is used to predict impending failure of a useful circuit or circuits in a host IC. Increasing the stress on the prognostic cell relative to the useful circuit shifts the failure distribution of the cell along the time axis. The relative amount of time between the useful circuit failure and prognostic cell trigger point is the “prognostic distance”. The prognostic distance is controlled by designing in the excess stress applied in test device(s), by setting the threshold for triggering in the comparison circuit or by both. Prediction accuracy is enhanced by using multiple test devices to oversample the underlying failure distribution and triggering the failure indicator when a certain fraction fail.
摘要翻译： 预测细胞用于预测主机IC中有用电路或电路的即将发生的故障。 相对于有用的电路增加对预后细胞的压力将沿着时间轴移动细胞的失效分布。 有用的电路故障和预后单元触发点之间的相对时间量是“预后距离”。 通过设计在测试装置中施加的过度应力，通过设置比较电路中的触发阈值或两者来控制预测距离。 通过使用多个测试设备来过滤基础故障分布并在某个分数失败时触发故障指示器来提高预测精度。
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8.发明授权
公开(公告)号：US4778258A
公开(公告)日：1988-10-18
申请号：US104452
申请日：1987-10-05
IPC分类号： G02F1/1368 , H01L27/12 , G02F1/13
CPC分类号： H01L27/12 , G02F1/1368 , Y10S359/90
摘要： A process for the fabrication of thin film field effect transistors in active matrix liquid crystal display devices includes the utilization of a protective, conductive tab disposed on a corner portion of the pixel electrodes. Electrical contact is made to the pixel electrodes not directly, but rather through a via opening in protective, insulative and amorphous silicon layers. The structure is particularly advantageous in that it permits the utilization of a wider range of gate and upper level metallization materials, particularly aluminum, whose etchants are otherwise found deleterious to pixel electrode material such as indium tin oxide. The structure of the present invention is seen to be readily fabricatable in accordance with high yield fabrication procedures.
摘要翻译： 在有源矩阵液晶显示装置中制造薄膜场效应晶体管的方法包括利用设置在像素电极的角部上的保护导电片。 不直接地对像素电极进行电接触，而是通过保护性，绝缘和非晶硅层中的通孔开口进行电接触。 该结构是特别有利的，因为其允许利用较宽范围的栅极和上层金属化材料，特别是铝，其蚀刻剂被认为对诸如氧化铟锡的像素电极材料有害。 本发明的结构被认为可以根据高产量制造方法容易地制造。
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公开(公告)号：US4224552A
公开(公告)日：1980-09-23
申请号：US974655
申请日：1978-12-22
申请人： Harold G. Parks
发明人： Harold G. Parks
CPC分类号： H01J29/66 , H01J29/806
摘要： An improved magnetic fine deflection system, for use in an electron beam optical system of the type having a single plate matrix lens, utilizes an orthogonal set of stacked deflection-field-generating conductors, with one stacked orthogonal pair of sheet conductors being positioned behind a target, upon which the electron beam is to be focused and deflected, and with a second orthogonal pair of sheet conductors positioned in front of the multi-apertured single plate matrix lens and having apertures in registration with the lenslets. The improved magnetic fine deflection system is utilized in an electron beam optical system having first means for forming a narrow beam of electrons and coarse deflection means associated with the first means for scanning the electron beam to each lenslet of the single plate matrix lens, for passage therethrough and into the magnetic fine deflection field.
摘要翻译： 用于具有单一平板矩阵透镜的类型的电子束光学系统中的改进的磁性精细偏转系统利用了一组叠置的偏转场产生导体的正交集合，其中一个堆叠的正交一对片状导体位于 目标，电子束将被聚焦和偏转，并且具有定位在多孔单板矩阵透镜之前的第二正交的一对片状导体，并且具有与小透镜对准的孔。 改进的磁性精细偏转系统被用于具有用于形成窄的电子束的第一装置和与第一装置相关的第一装置的电子束光学系统，该第一装置用于将电子束扫描到单一平板矩阵透镜的每个小透镜，以通过 穿过并进入磁性微偏转场。
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10.发明授权N.sup.+ amorphous silicon thin film transistors for matrix addressed liquid crystal displays 失效用于矩阵寻址液晶显示器的N +非晶硅薄膜晶体管
公开(公告)号：US4933296A
公开(公告)日：1990-06-12
申请号：US761938
申请日：1985-08-02
IPC分类号： H01L29/78 , G02F1/133 , G02F1/136 , G02F1/1368 , G09F9/35 , H01L21/285 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/45 , H01L29/786
CPC分类号： H01L29/66765 , G02F1/1368 , H01L21/28512 , H01L27/124 , H01L29/458 , G02F2202/103
摘要： A thin film FET switching element, particularly useful in liquid crystal displays (LCDs) employs particular materials and is fabricated via a particular process to ensure chemical compatibility and the formation of good electrical contact to an amorphous silicon layer while also producing FETs with desirable electrical properties for LCDs. These materials include the use of titanium as a gate electrode material and the use of N.sup.+ amorphous silicon as a material to enhance electrical contact between molybdenum source and drain pads and an underlying layer of amorphous silicon. The process of the present invention provides enhanced fabrication yield and device performance.
摘要翻译： 特别适用于液晶显示器（LCD）的薄膜FET开关元件采用特定材料，并通过特定工艺制造，以确保化学相容性和与非晶硅层形成良好的电接触，同时还产生具有所需电性能的FET 用于LCD。 这些材料包括使用钛作为栅极电极材料，以及使用N +非晶硅作为材料来增强钼源和漏极焊盘之间的电接触以及下一层非晶硅。 本发明的方法提供了增强的制造产量和装置性能。
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