公开(公告)号：US06396253B1

公开(公告)日：2002-05-28

申请号：US09443733

申请日：1999-11-19

Applicant: Scott W. Petrick ,  Matthew E. Ellis ,  Didier A. Verot ,  Donald E. Castleberry

Inventor： Scott W. Petrick ,  Matthew E. Ellis ,  Didier A. Verot ,  Donald E. Castleberry

IPC: G01R3102

CPC classification number: H04N5/367 ,  H04N5/32 ,  H04N17/002

Abstract: A method for detecting cut data lines in an imaging array having a detector including an array of pixels for measuring radiation, and a plurality of data line contacts is provided. The method includes the steps of initializing pixels of the imaging array which includes a plurality of data lines including at least one uncut data line and at least one cut data line, wherein each cut data line is electrically connected to at least one of the plurality of data line contacts and at least one uncommitted contact. The method further includes determining a signal level for the uncut data lines, measuring a signal level of each data line in the plurality of data lines, and determining a number of cut data lines and a number of uncut data lines by using the signal levels received from each data line in the plurality of data.

Abstract translation: 一种用于检测具有检测器的成像阵列中的切割数据线的方法，所述检测器包括用于测量辐射的像素阵列，以及多个数据线触点。 该方法包括以下步骤：初始化成像阵列的像素，该像素包括包括至少一个未切割数据线和至少一个切割数据线的多个数据线，其中每个切割数据线电连接到多个 数据线触点和至少一个未提交的触点。 该方法还包括确定未切割数据线的信号电平，测量多条数据线中的每条数据线的信号电平，以及通过使用所接收的信号电平来确定数量的切割数据线和多条未切割的数据线 从多个数据中的每个数据线。

公开(公告)号：US4804953A

公开(公告)日：1989-02-14

申请号：US97247

申请日：1987-09-16

Applicant: Donald E. Castleberry

Inventor： Donald E. Castleberry

IPC: G09G3/20 ,  G02F1/1335 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/36

CPC classification number: G02F1/1362 ,  G02F1/1368 ,  G02F1/133512 ,  G02F2001/13629 ,  G02F2202/103

Abstract: Redundancy is provided in the data and gate lines of the liquid crystal display device for improved reliability and greater fabrication yield. The data lines in particular are preferably fabricated in a multilayer structure with two conductive layers sandwiching a narrow insulating strip. The presence of the insulating strip permits the upper conductive line to be formed without step jumps which can exhibit a tendency for poor electrical connection. The upper and lower conductive layers of the data line are in contact for the length of the lower data line, contact being made on either side of the narrower insulating strip. Similar redundancy, without the necessity of providing an intermediary insulating layer is also provided for the gate lines. The redundancy provided in the present invention is particularly suitable for fabrication methods employed in thin film FET driven LCD devices.

Abstract translation: 在液晶显示装置的数据和栅极线中提供冗余，以提高可靠性和更高的制造成品率。 数据线特别优选地制造成具有夹着窄绝缘条的两个导电层的多层结构。 绝缘条的存在允许形成上导电线，而不会出现可能表现出差的电连接的趋势的阶跃跳跃。 数据线的上导电层和下导电层在下数据线的长度上接触，接触在较窄的绝缘条的任一侧上进行。 也为栅极线提供了类似的冗余，而不需要提供中间绝缘层。 本发明中提供的冗余特别适用于薄膜FET驱动LCD器件中使用的制造方法。

公开(公告)号：US4212048A

公开(公告)日：1980-07-08

申请号：US916137

申请日：1978-06-16

Applicant: Donald E. Castleberry

Inventor： Donald E. Castleberry

IPC: F21V8/00 ,  G02F1/13357 ,  G02F1/139 ,  F21V9/14 ,  F21V7/00 ,  G02F1/13

CPC classification number: G02B6/0056 ,  G02F1/133615 ,  G02F1/13362 ,  G02F1/13725 ,  G02F2001/133616 ,  G02F2203/02

Abstract: A device for illuminating, as well as enhancing contrast of, reflective dichroic liquid crystal displays utilizes a polarizing member extending across the thickness of a wedge illuminator. The light emitted from the wedge illuminator is polarized in a single direction, perpendicular to the elongated direction of the dichroic dye molecules in the light-transmitting areas of the display cell.

Abstract translation: 用于照亮并增强反射二向色液晶显示器的对比度的装置利用延伸穿过楔形照明器的厚度的偏振构件。 从楔形照明器发射的光在显示单元的透光区域中垂直于二向色染料分子的细长方向的单一方向上极化。

公开(公告)号：US5489551A

公开(公告)日：1996-02-06

申请号：US376209

申请日：1995-01-20

Applicant: Donald E. Castleberry

Inventor： Donald E. Castleberry

IPC: H01L31/0224 ,  H01R4/04 ,  H01R43/02 ,  H05K3/32 ,  H05K3/36 ,  H01L21/283 ,  H01L21/60

CPC classification number: H05K3/321 ,  H01L31/0224 ,  H01R43/0256 ,  H01R4/04 ,  H01R43/0221 ,  H05K2201/0108 ,  H05K2201/0323 ,  H05K2201/10136 ,  H05K2203/107 ,  H05K2203/1136 ,  H05K3/361 ,  Y10T29/49144

Abstract: A method of fabricating a high density thin film circuit includes the step of bonding a high density connector having a plurality of electrical connection lines with a wafer having a plurality of electrical contact pads arranged in a pattern with a pitch less than about 100 .mu.m so that an electrical coupling is formed between the wafer contact pads and connector electrical connection lines. The step of forming the electrical coupling comprises pyrolysis of an adhesive disposed between the high density connector and said wafer. The electrical coupling between the contact pads and electrical connection lines is formed by directing a laser beam on the area in which the electrical coupling is to be formed so as to cause thermal decomposition of the adhesive to form a conductive carbon material; portions of the wafer contact pads and the connector electrical connection lines are also welded to the conductive carbon material.

Abstract translation: 一种制造高密度薄膜电路的方法包括将具有多个电连接线的高密度连接器与具有多个电接触焊盘的晶片接合的步骤，该多个电接触焊盘以小于约100μm的间距排列， 在晶片接触焊盘和连接器电连接线之间形成电耦合。 形成电耦合的步骤包括热分解设置在高密度连接器和所述晶片之间的粘合剂。 接触焊盘和电连接线之间的电耦合通过将激光束引导到要形成电耦合的区域上以使粘合剂热分解形成导电碳材料而形成; 晶片接触焊盘和连接器电连接线的部分也焊接到导电碳材料上。

公开(公告)号：US4873516A

公开(公告)日：1989-10-10

申请号：US287670

申请日：1988-12-22

Applicant: Donald E. Castleberry

Inventor： Donald E. Castleberry

IPC: G09G3/20 ,  G09G3/36

CPC classification number: G09G3/3648 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2320/0209 ,  G09G3/2011

Abstract: In a liquid crystal display, and more particularly, in a thin film transistor matrix addressed liquid crystal display, a method and means are provided for assuring the presence of a constant RMS voltage waveform on the data lines. This eliminates uncertainty in the voltage levels on a pixel element caused by parasitic capacitance effects between the data lines and the pixel electrodes. The present invention is also particularly applicable to both binary level and gray scale level devices. Means for carrying out the present method are illustrated in both analog and digital form.

Abstract translation: 在液晶显示器中，更具体地说，在薄膜晶体管矩阵寻址液晶显示器中，提供了一种方法和装置，用于确保在数据线上存在恒定的RMS电压波形。 这消除了由数据线和像素电极之间的寄生电容效应引起的像素元件上的电压电平的不确定性。 本发明还特别适用于二进制级和灰度级装置。 用于执行本方法的手段以模拟和数字形式示出。

公开(公告)号：US4688896A

公开(公告)日：1987-08-25

申请号：US707996

申请日：1985-03-04

Applicant: Donald E. Castleberry

Inventor： Donald E. Castleberry

IPC: H01L27/12 ,  G02F1/13 ,  G02F1/133 ,  G02F1/1343 ,  G02F1/1362 ,  G09G3/20 ,  G09G3/36 ,  H01L29/78 ,  H01L29/786 ,  G01C11/06

CPC classification number: G02F1/1309 ,  G09G3/20 ,  G09G3/36 ,  G02F2001/136272 ,  G09G2330/08

Abstract: An enhanced manufacturing yield of a high resolution, high accuracy information conversion device, such as a liquid crystal display, is attained through incorporation into the device of auxiliary address lines. Such auxiliary address lines are used to provide electrical communication with portions of main address lines that, due to the presence of electrical open circuits, would otherwise be electrically isolated. Each auxiliary address line crosses over multiple main address lines and can be electrically shorted to any such main address line to provide electrical communication therewith. The ratio of auxiliary address lines to main address lines is accordingly low, such as 1:10 or less, for example.

Abstract translation: 高分辨率，高精度信息转换装置如液晶显示器的增强的制造成品通过结合到辅助地址线的装置中而获得。 这样的辅助地址线用于与主地址线的部分电连接，由于存在电开路，否则将被电隔离。 每个辅助地址线跨越多个主地址线，并且可以与任何这样的主地址线电短路以提供与其的电通信。 因此，辅助地址线与主地址线的比例相当低，例如1:10或更小。

公开(公告)号：US4161766A

公开(公告)日：1979-07-17

申请号：US799298

申请日：1977-05-23

Applicant: Donald E. Castleberry ,  Wesley K. Waldron

Inventor： Donald E. Castleberry ,  Wesley K. Waldron

IPC: H03K17/96 ,  H01G7/00

CPC classification number: H03K17/962

Abstract: A laminated capacitive touch-pad having a thin film touch-plate electrode deposited upon a first (exterior) surface of a first, relatively thin dielectric layer and having spaced transmitter and receiver electrodes deposited upon a second surface of the first layer within the outline of and opposite to the touch electrode, with a relatively thick backing layer of dielectric material laminated upon the second surface to provide a total thickness, as measured between the furthest opposed surfaces of the first and second layers, as required for high voltage insulation purposes and to provide additional impact strength. The touch, transmitter and receiver electrodes may be of thin film construction.

Abstract translation: 具有薄膜触摸板电极的层压电容式触摸板，其沉积在第一相对较薄的电介质层的第一（外部）表面上，并且具有间隔的发射器和接收器电极，其沉积在第一层的第二表面内 并且与触摸电极相对，具有层叠在第二表面上的相对厚的介电材料背衬层，以提供如第一和第二层的最远的相对表面之间测量的总厚度，这是为了高电压绝缘目的所需要的，并且 提供额外的冲击强度。 触摸，发射器和接收器电极可以是薄膜结构。

公开(公告)号：US5500376A

公开(公告)日：1996-03-19

申请号：US383622

申请日：1995-02-06

Applicant: Ahmad N. Ishaque ,  Donald E. Castleberry

Inventor： Ahmad N. Ishaque ,  Donald E. Castleberry

IPC: H01L31/107 ,  H01L31/18

CPC classification number: H01L31/107 ,  Y10S438/965

Abstract: A method of forming a planar photosensitive device, such as an array of APDs, includes the steps of doping a substantially planar block of n type semiconductor material with a p type dopant in accordance with a selected pattern to form a plurality of p type wells in the block surrounded by a foundation of n type semiconductor material. Each p type well corresponds to an APD pixel and is disposed so as to respectively adjoin a first surface of the block and such that a respective p-n junction is formed between the p type material in the well and the n type material foundation. Each APD pixel further comprises depletion layer profile modification means such that the peak surface electric field of the p-n junction in each well is substantially less than the bulk electric field of the same p-n junction. One type of depletion layer profile modification means is an peripheral doped region of p material disposed around each respective well; an alternative depletion layer profile modification means is a respective isolation moat around each well so as to separate p type material in the well from n type material in the foundation except along a parallel plane segment of the p-n junction.

Abstract translation: 形成诸如APD阵列的平面光敏器件的方法包括以下步骤：根据所选择的图案，将具有ap型掺杂剂的n型半导体材料的基本上平面的块掺杂以形成多个p型阱， 由n型半导体材料的基础包围的块。 每个p型阱对应于APD像素并且被布置成分别邻接块的第一表面并且使得在阱中的p型材料和n型材料基底之间形成相应的p-n结。 每个APD像素还包括耗尽层轮廓修改装置，使得每个阱中的p-n结的峰面电场基本上小于相同p-n结的体电场。 一种类型的耗尽层轮廓修改装置是围绕每个相应的孔设置的p材料的外围掺杂区域; 替代的耗尽层轮廓修改装置是围绕每个井的相应的隔离护环，以便将井中的p型材料与基础中的n型材料分开，除了沿着p-n结的平行平面段。

公开(公告)号：US5446308A

公开(公告)日：1995-08-29

申请号：US223397

申请日：1994-04-04

Applicant: Dante E. Piccone ,  Ahmad N. Ishaque ,  Donald E. Castleberry ,  Henri M. Rougeot ,  Peter Menditto

Inventor： Dante E. Piccone ,  Ahmad N. Ishaque ,  Donald E. Castleberry ,  Henri M. Rougeot ,  Peter Menditto

IPC: H01L27/146 ,  H01L31/107 ,  H01L327/146

CPC classification number: H01L27/14643 ,  H01L31/107 ,  Y10S438/965

Abstract: A method of forming a planar semiconductor device, such as an array of APDs, includes the steps of doping a substantially planar block of n type semiconductor material with a p type dopant in accordance with a selected pattern to form a plurality of n type wells in the block surrounded by a foundation of p type semiconductor material. Each n type well is disposed so as to respectively adjoin a first surface of the block and such that a respective p-n junction is formed between the n type material in the well and the p type material foundation. The n type semiconductor material in each well has a substantially constant concentration of n type dopant throughout the n type material; the concentration of p type dopant in the foundation has a positive gradient extending from the p-n junction towards the second surface such that the peak surface electric field of the p-n junction in each well is less than the bulk electric field of the same p-n junction.

Abstract translation: 形成诸如APD阵列的平面半导体器件的方法包括以下步骤：根据所选择的图案，掺杂具有ap型掺杂剂的n型半导体材料的基本上平面的块，以在其中形成多个n型阱 由p型半导体材料的基础包围的块。 每个n型阱被设置成分别邻接块的第一表面，并且使得在井中的n型材料和p型材料基础之间形成相应的p-n结。 每个阱中的n型半导体材料在整个n型材料中具有基本恒定的n型掺杂剂的浓度; 基底中p型掺杂剂的浓度具有从p-n结朝向第二表面延伸的正梯度，使得每个阱中的p-n结的峰值表面电场小于相同p-n结的体电场。

公开(公告)号：US5438217A

公开(公告)日：1995-08-01

申请号：US235052

申请日：1994-04-29

Applicant: Ahmad N. Ishaque ,  Donald E. Castleberry

Inventor： Ahmad N. Ishaque ,  Donald E. Castleberry

IPC: H01L31/107 ,  H01L27/14 ,  H01L31/00

CPC classification number: H01L31/107 ,  Y10S438/965

Abstract: A planar photosensitive device, such as an array of APDs, includes a planar block of n type semiconductor material having a plurality of p type wells in the block surrounded by a foundation of n type semiconductor material. Each p type well corresponds to an APD pixel and is disposed so as to respectively adjoin a first surface of the block and such that a respective p-n junction is formed between the p type material in the well and the n type material foundation. Each APD pixel further comprises depletion layer profile modification means such that the peak surface electric field of the p-n junction in each well is substantially less than the bulk electric field of the same p-n junction. One type of depletion layer profile modification means is a peripheral doped region of p material disposed around each respective well; an alternative depletion layer profile modification means is a respective isolation moat around each well so as to separate p type material in the well from n type material in the foundation except along a parallel plane segment of the p-n junction.

Abstract translation: 诸如APD阵列的平面光敏器件包括n型半导体材料的平面块，其在由n型半导体材料的基础包围的块中具有多个p型阱。 每个p型阱对应于APD像素并且被布置成分别邻接块的第一表面并且使得在阱中的p型材料和n型材料基底之间形成相应的p-n结。 每个APD像素还包括耗尽层轮廓修改装置，使得每个阱中的p-n结的峰面电场基本上小于相同p-n结的体电场。 一种类型的耗尽层轮廓修改装置是围绕每个相应的孔设置的p材料的外围掺杂区域; 替代的耗尽层轮廓修改装置是围绕每个井的相应的隔离护环，以便将井中的p型材料与基础中的n型材料分开，除了沿着p-n结的平行平面段。