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    Structure to reduce etching residue
    4.
    发明授权
    Structure to reduce etching residue 有权
    结构减少蚀刻残留

    公开(公告)号：US08217499B2

    公开(公告)日：2012-07-10

    申请号：US12952485

    申请日：2010-11-23

    Applicant: Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Chung-Ying Yang

    Inventor： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Chung-Ying Yang

    IPC: H01L23/544

    CPC classification number: H01L21/31144 ,  H01L21/32139 ,  H01L23/585 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal corner may be replaced with an orthogonal intersection between two trenches. The layout reduces the intersection area as well as the possibility of having partially etched materials left at the intersection area. The structure also includes an alternative way to fill the intersection area with either an un-etched small trapezoidal area or multiple un-etched square areas, so that the opening area at the intersection point is reduced and the possibility of having partially etched materials is reduced too.

    Abstract translation: 描述了用于减少部分蚀刻的材料的结构。 该结构包括两个沟槽之间的交叉区域的布局。 首先，具有梯形角的大交叉区域可以用两个沟槽之间的正交交替来代替。 布局减少了交叉区域以及在交叉区域留下部分蚀刻的材料的可能性。 该结构还包括用未蚀刻的小梯形区域或多个未蚀刻的正方形区域填充交叉区域的替代方法，使得交点处的开口面积减小，并且部分蚀刻材料的可能性降低 太。

    Seal ring structure in semiconductor devices
    5.
    发明授权
    Seal ring structure in semiconductor devices 有权
    半导体器件中的密封圈结构

    公开(公告)号：US08253217B2

    公开(公告)日：2012-08-28

    申请号：US12816454

    申请日：2010-06-16

    Applicant: Hsien-Wei Chen ,  Chung-Ying Yang

    Inventor： Hsien-Wei Chen ,  Chung-Ying Yang

    IPC: H01L23/52 ,  H01L21/76

    CPC classification number: H01L23/585 ,  H01L23/3157 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

    Abstract: The present disclosure provides a semiconductor device that includes a substrate having a seal ring region and a circuit region, a plurality of dummy gates disposed over the seal ring region of the substrate, and a seal ring structure disposed over the plurality of dummy gates in the seal ring region. A method of fabricating a semiconductor device is also provided, the method including providing a substrate having a seal ring region and a circuit region, forming a plurality of dummy gates over the seal ring region of the substrate, and forming a seal ring structure over the plurality of dummy gates over the seal ring region.

    Abstract translation: 本公开提供一种半导体器件，其包括具有密封环区域和电路区域的衬底，设置在衬底的密封环区域上方的多个虚拟栅极以及设置在多个虚拟栅极中的密封环结构 密封圈区域。 还提供了制造半导体器件的方法，所述方法包括提供具有密封环区域和电路区域的衬底，在衬底的密封环区域上形成多个虚拟栅极，并在衬底上形成密封环结构 在密封圈区域上的多个虚拟门。

    Structure to Reduce Etching Residue
    7.
    发明申请
    Structure to Reduce Etching Residue 有权
    减少蚀刻残渣的结构

    公开(公告)号：US20120126359A1

    公开(公告)日：2012-05-24

    申请号：US12952485

    申请日：2010-11-23

    Applicant: Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Chung-Ying Yang

    Inventor： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Chung-Ying Yang

    IPC: H01L29/06 ,  H01L21/76

    CPC classification number: H01L21/31144 ,  H01L21/32139 ,  H01L23/585 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal corner may be replaced with an orthogonal intersection between two trenches. The layout reduces the intersection area as well as the possibility of having partially etched materials left at the intersection area. The structure also includes an alternative way to fill the intersection area with either an un-etched small trapezoidal area or multiple un-etched square areas, so that the opening area at the intersection point is reduced and the possibility of having partially etched materials is reduced too.

    Abstract translation: 描述了用于减少部分蚀刻的材料的结构。 该结构包括两个沟槽之间的交叉区域的布局。 首先，具有梯形角的大交叉区域可以用两个沟槽之间的正交交替来代替。 布局减少了交叉区域以及在交叉区域留下部分蚀刻的材料的可能性。 该结构还包括用未蚀刻的小梯形区域或多个未蚀刻的正方形区域填充交叉区域的替代方法，使得交点处的开口面积减小，并且部分蚀刻材料的可能性降低 太。

    SEAL RING STRUCTURE IN SEMICONDUCTOR DEVICES
    8.
    发明申请
    SEAL RING STRUCTURE IN SEMICONDUCTOR DEVICES 有权
    半导体器件密封环结构

    公开(公告)号：US20110309465A1

    公开(公告)日：2011-12-22

    申请号：US12816454

    申请日：2010-06-16

    Applicant: Hsien-Wei Chen ,  Chung-Ying Yang

    Inventor： Hsien-Wei Chen ,  Chung-Ying Yang

    IPC: H01L29/06 ,  H01L21/76

    CPC classification number: H01L23/585 ,  H01L23/3157 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

    Abstract: The present disclosure provides a semiconductor device that includes a substrate having a seal ring region and a circuit region, a plurality of dummy gates disposed over the seal ring region of the substrate, and a seal ring structure disposed over the plurality of dummy gates in the seal ring region. A method of fabricating a semiconductor device is also provided, the method including providing a substrate having a seal ring region and a circuit region, forming a plurality of dummy gates over the seal ring region of the substrate, and forming a seal ring structure over the plurality of dummy gates over the seal ring region.

    Abstract translation: 本公开提供一种半导体器件，其包括具有密封环区域和电路区域的衬底，设置在衬底的密封环区域上方的多个虚拟栅极以及设置在多个虚拟栅极中的密封环结构 密封圈区域。 还提供了制造半导体器件的方法，所述方法包括提供具有密封圈区域和电路区域的衬底，在衬底的密封环区域上形成多个虚拟栅极，并在衬底上形成密封环结构 在密封圈区域上的多个虚拟门。

    Guard ring design structure for semiconductor devices
    10.
    发明授权
    Guard ring design structure for semiconductor devices 有权
    半导体器件的保护环设计结构

    公开(公告)号：US09478505B2

    公开(公告)日：2016-10-25

    申请号：US13445229

    申请日：2012-04-12

    Applicant: Hsien-Wei Chen ,  Chung-Ying Yang

    Inventor： Hsien-Wei Chen ,  Chung-Ying Yang

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/58 ,  H01L23/528 ,  H01L23/31

    CPC classification number: H01L23/585 ,  H01L23/3171 ,  H01L23/5283 ,  H01L23/562 ,  H01L23/564 ,  H01L2224/02165 ,  H01L2224/02166 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells.

    Abstract translation: 用于半导体器件的定制密封环由多个密封环电池形成，所述多个密封环电池被选择和布置以产生密封环设计。 这些电池包括耦合到地的第一个电池和不耦合到地的第二个电池。 与第一密封环电池相比，没有耦合到地面的第二电池在其内部包括更高密度的金属特征。 可能存在于第二密封环单元的内部的虚拟金属通孔和其它金属特征不存在于耦合到地的第一密封环单元的内部。 密封环设计可以包括各种布置，包括不同密封环单元的交替和重复序列。

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