公开(公告)号：US20080142994A1

公开(公告)日：2008-06-19

申请号：US12036928

申请日：2008-02-25

Applicant: Szu Wei Lu ,  Hsin-Hui Lee ,  Chung Yu Wang ,  Mirng-Ji Lii

Inventor： Szu Wei Lu ,  Hsin-Hui Lee ,  Chung Yu Wang ,  Mirng-Ji Lii

IPC: H01L23/52

CPC classification number: H01L24/10 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00011 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81805 ,  H01L2924/013

Abstract: A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with the first conductive pad, the first interface having a first linear dimension; the bump has a second interface with the second conductive pad, the second interface having a second linear dimension; and wherein the ratio of the first linear dimension and the second linear dimension is between about 0.7 and about 1.7.

Abstract translation: 半导体封装组件包括半导体衬底上的第一导电焊盘; 封装衬底上的第二导电焊盘; 物理耦合在所述第一导电焊盘和所述第二导电焊盘之间的突起，其中所述突起基本上是无铅或高含铅的; 所述凸块具有与所述第一导电焊盘的第一界面，所述第一界面具有第一线性尺寸; 所述凸块具有与所述第二导电焊盘的第二接口，所述第二接口具有第二线性尺寸; 并且其中所述第一线性尺寸和所述第二线性尺寸的比率在约0.7和约1.7之间。

公开(公告)号：US08642390B2

公开(公告)日：2014-02-04

申请号：US12726317

申请日：2010-03-17

Applicant: Chung Yu Wang ,  Jiann-Jong Wang

Inventor： Chung Yu Wang ,  Jiann-Jong Wang

IPC: H01L21/00 ,  H01L21/46

CPC classification number: H01L21/6836 ,  H01L23/3114 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05655 ,  H01L2224/0568 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Organic-adhesive tapes are often used to secure and protect the bumps during wafer processing after bump formation. While residual organic-adhesive tape may remain on the wafer after tape de-lamination, applying a bump template layer on the bumps before laminating the tape allows any residue to be removed afterwards and results in a residue-free wafer.

Abstract translation: 有机胶带通常用于在凸块形成后的晶片加工过程中固定和保护凸块。 虽然残留的有机粘合带可能在胶带去层压之后残留在晶片上，但是在层压胶带之前在凸块上施加凸块模板层可以使之后去除任何残留物，并产生无残留的晶片。

公开(公告)号：US20130122689A1

公开(公告)日：2013-05-16

申请号：US13298014

申请日：2011-11-16

Applicant: Chung Yu Wang ,  Jui-Pin Hung ,  Chih-Hao Chen ,  Chun-Hsing Su ,  Yi-Chao Mao ,  Kung-Chen Yeh ,  Yi-Lin Tsai ,  Ying-Tz Hung ,  Chin-Fu Kao ,  Shih-Yi Syu ,  Chin-Chuan Chang ,  Hsien-Wen Liu ,  Long Hua Lee

Inventor： Chung Yu Wang ,  Jui-Pin Hung ,  Chih-Hao Chen ,  Chun-Hsing Su ,  Yi-Chao Mao ,  Kung-Chen Yeh ,  Yi-Lin Tsai ,  Ying-Tz Hung ,  Chin-Fu Kao ,  Shih-Yi Syu ,  Chin-Chuan Chang ,  Hsien-Wen Liu ,  Long Hua Lee

IPC: H01L21/78

CPC classification number: H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/11002 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/00

Abstract: A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.

Abstract translation: 一种方法包括在包括多个管芯的复合晶片上执行切割，其中当执行切割步骤时，复合晶片结合在载体上。 在切割步骤之后，将复合晶片安装在带上。 然后将载体从复合晶片和第一带去粘合。

公开(公告)号：US20130075937A1

公开(公告)日：2013-03-28

申请号：US13246556

申请日：2011-09-27

Applicant: Chung Yu Wang ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

Inventor： Chung Yu Wang ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/28 ,  H01L21/50 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.

Abstract translation: 用于在晶片插入件上的模具上进行模制的方法和装置。 一种方法包括接收具有管芯侧面和相对侧的插入件组件，所述插入件组件包括安装在所述插入件的裸片侧上的两个或多个集成电路管芯，所述插入器组件具有形成在所述插入件的裸片侧上的两个或更多个集成 电路模具; 在所述两个或更多个集成电路管芯之间的空间之一中在所述插入器组件的管芯侧上安装至少一个应力释放特征; 以及使用模具化合物模制所述集成电路模具，围绕所述两个或更多个集成电路管芯的所述模具化合物以及所述至少一个应力释放特征。 公开了一种装置，其集成电路安装在插入件的裸片侧，集成电路之间的应力消除特征和集成电路上的模具化合物。

公开(公告)号：US08183580B2

公开(公告)日：2012-05-22

申请号：US12715872

申请日：2010-03-02

Applicant: Chung Yu Wang

Inventor： Chung Yu Wang

IPC: H01L27/15 ,  H01L31/12 ,  H01L33/00

CPC classification number: H01L33/62 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/49107 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A light-emitting device (LED) package component includes an LED chip and a carrier chip. The carrier chip includes a first bond pad and a second bond pad on a surface of the carrier chip and bonded onto the LED chip through flip-chip bonding, and a third bond pad and a fourth bond pad on the surface of the carrier chip and electrically connected to the first bond pad and the second bond pad, respectively. The first bond pad and the second bond pad are on a same side of the carrier chip facing the LED chip. The carrier chip further includes at least one through substrate via (TSV) connected to the first and second bond pads.

Abstract translation: 发光器件（LED）封装部件包括LED芯片和载体芯片。 载体芯片包括在载体芯片的表面上的第一接合焊盘和第二接合焊盘，并通过倒装芯片接合结合到LED芯片上，以及在载体芯片的表面上的第三接合焊盘和第四接合焊盘， 电连接到第一接合焊盘和第二接合焊盘。 第一接合焊盘和第二接合焊盘位于与芯片相对的载体芯片的同一侧。 载体芯片还包括连接到第一和第二接合焊盘的至少一个贯穿衬底通孔（TSV）。

公开(公告)号：US20110215360A1

公开(公告)日：2011-09-08

申请号：US12715838

申请日：2010-03-02

Applicant: Chung Yu Wang

Inventor： Chung Yu Wang

IPC: H01L33/62 ,  H01L33/00

CPC classification number: H01L33/62 ,  H01L24/17 ,  H01L33/486 ,  H01L33/54 ,  H01L33/642 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49107 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light-emitting device (LED) package component includes an LED chip having a first active bond pad and a second active bond pad. A carrier chip is bonded onto the LED chip through flip-chip bonding. The carrier chip includes a first active through-substrate via (TSV) and a second active TSV connected to the first and the second active bond pads, respectively. The carrier chip further includes a dummy TSV therein, which is electrically coupled to the first active bond pad, and is configured not to conduct any current when a current flows through the LED chip.

Abstract translation: 发光器件（LED）封装部件包括具有第一有源接合焊盘和第二有源接合焊盘的LED芯片。 载体芯片通过倒装芯片接合结合到LED芯片上。 载体芯片包括分别连接到第一和第二有源接合焊盘的第一有源通过衬底通孔（TSV）和第二有源TSV。 载体芯片还包括其中的虚拟TSV，其电耦合到第一有源接合焊盘，并且被配置为在电流流过LED芯片时不导通任何电流。

公开(公告)号：US06774026B1

公开(公告)日：2004-08-10

申请号：US10177912

申请日：2002-06-20

Applicant: Chung Yu Wang ,  Chender Huang ,  Pei Haw Tsao ,  Ken Chen ,  Hank Huang

Inventor： Chung Yu Wang ,  Chender Huang ,  Pei Haw Tsao ,  Ken Chen ,  Hank Huang

IPC: H01L2144

CPC classification number: H01L24/11 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00014

Abstract: Low stress concentration solder bumps are created on a semiconductor wafer by the removal of metal oxides of under bump metallurgy, (UBM). The removal of the oxides from the circular edge of the UBM allow the solder of the solder bump to wet the sides of the UBM, mainly the plated portion, thereby resulting in a solder bump structure with a filled undercut. This results in a lower stress concentration solder bump structure. This solder bump structure is obtained after the solder bumps have been reflowed on the wafer.

Abstract translation: 通过去除不良冲击冶金（UBM）的金属氧化物，在半导体晶片上形成低应力集中焊料凸块。 从UBM的圆形边缘去除氧化物允许焊料凸块的焊料润湿UBM的侧面，主要是镀覆部分，从而导致具有填充底切的焊料凸块结构。 这导致较低的应力集中焊料凸块结构。 在焊料凸起已经在晶片上回流之后获得该焊料凸点结构。

公开(公告)号：US06770958B2

公开(公告)日：2004-08-03

申请号：US10462268

申请日：2003-06-16

Applicant: Chung Yu Wang ,  Chender Huang ,  Pei-Haw Tsao ,  Ken Chen ,  Hank Huang

Inventor： Chung Yu Wang ,  Chender Huang ,  Pei-Haw Tsao ,  Ken Chen ,  Hank Huang

IPC: H01L23495

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13007 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: An under bump metallurgy (UBM) structure is described. Two UBM mask processes are utilized. First, a top layer of copper (Cu) and/or a middle layer of nickel-vanadium (NiV) or chrome-copper (CrCu) is personalized by standard photoprocessing and etching steps utilizing a bump based size mask. This is followed by patterning an underlying seed layer with a second, larger mask, thereby preventing damage to the aluminum cap and seed layer undercut during the etching process.

Abstract translation: 描述了凸块下冶金（UBM）结构。 利用两个UBM掩模过程。 首先，通过使用基于凸块的尺寸掩模的标准光刻处理和蚀刻步骤对铜（Cu）和/或镍 - 钒（NiV）或铬 - 铜（CrCu）的中间层进行个性化的顶层。 之后，用第二个较大的掩模对下面的种子层进行图案化，从而防止在蚀刻过程期间对铝盖和籽晶层的破坏。

公开(公告)号：US08816495B2

公开(公告)日：2014-08-26

申请号：US13398672

申请日：2012-02-16

Applicant: Chung Yu Wang ,  Shih-Yi Syu ,  Jing-Cheng Lin

Inventor： Chung Yu Wang ,  Shih-Yi Syu ,  Jing-Cheng Lin

IPC: H01L23/34

CPC classification number: H01L23/433 ,  H01L21/563 ,  H01L23/147 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A device includes a package component, and a die over and bonded to the package component. The die includes a substrate. A heat sink is disposed over and bonded to a back surface of the substrate through direct bonding.

Abstract translation: 一种装置包括一个封装部件和一个模具，并结合到封装部件上。 芯片包括基板。 散热器通过直接接合设置在基板的背面上并结合到基板的背面。

公开(公告)号：US08629043B2

公开(公告)日：2014-01-14

申请号：US13298014

申请日：2011-11-16

Applicant: Chung Yu Wang ,  Jui-Pin Hung ,  Chih-Hao Chen ,  Chun-Hsing Su ,  Yi-Chao Mao ,  Kung-Chen Yeh ,  Yi-Lin Tsai ,  Ying-Tz Hung ,  Chin-Fu Kao ,  Shih-Yi Syu ,  Chin-Chuan Chang ,  Hsien-Wen Liu ,  Long Hua Lee

Inventor： Chung Yu Wang ,  Jui-Pin Hung ,  Chih-Hao Chen ,  Chun-Hsing Su ,  Yi-Chao Mao ,  Kung-Chen Yeh ,  Yi-Lin Tsai ,  Ying-Tz Hung ,  Chin-Fu Kao ,  Shih-Yi Syu ,  Chin-Chuan Chang ,  Hsien-Wen Liu ,  Long Hua Lee

IPC: H01L21/78

CPC classification number: H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/11002 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/00

Abstract: A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.

Abstract translation: 一种方法包括在包括多个管芯的复合晶片上执行切割，其中当执行切割步骤时，复合晶片结合在载体上。 在切割步骤之后，将复合晶片安装在带上。 然后将载体从复合晶片和第一带去粘合。