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公开(公告)号：US08518742B1
公开(公告)日：2013-08-27
申请号：US13046903
申请日：2011-03-14
申请人： Chenglin Liu , Shiann-Ming Liou , Albert Wu
发明人： Chenglin Liu , Shiann-Ming Liou , Albert Wu
IPC分类号： H01L21/00
CPC分类号： H01L23/50 , H01L23/49531 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48111 , H01L2224/48137 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2225/06562 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H04N5/4401 , H04N21/426 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A packaged semiconductor includes inner bond fingers, at least first and second semiconductor dies, and an interposer. The packaged semiconductor further includes wiring between the first and second semiconductor dies and the inner bond fingers, wiring between the interposer and the inner bond fingers, and wiring between the interposer and the first and second semiconductor dies. The wiring between the interposer and the first and second semiconductor dies thereby reduces the count of inner bond fingers needed for the wiring between the first and second semiconductor dies and the inner bond fingers. The interposer further provides indirect access to the inner bond fingers when the inner bond fingers are inaccessible by the first and second semiconductor dies.
摘要翻译： 封装半导体包括内键指，至少第一和第二半导体管芯，以及插入件。 封装半导体还包括第一和第二半导体管芯与内部接合点之间的布线，插入件与内部接合指状物之间的布线以及插入件与第一和第二半导体管芯之间的布线。 插入器与第一和第二半导体管芯之间的布线因此减少了第一和第二半导体管芯与内部接合点之间的布线所需的内部接合指的数量。 当内键指不能被第一和第二半导体管芯访问时，插入件进一步提供对内部键合指的间接访问。
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公开(公告)号：US07911053B2
公开(公告)日：2011-03-22
申请号：US12105235
申请日：2008-04-17
申请人： Chenglin Liu , Shiann-Ming Liou , Albert Wu
发明人： Chenglin Liu , Shiann-Ming Liou , Albert Wu
IPC分类号： H01L23/34
CPC分类号： H01L23/50 , H01L23/49531 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48111 , H01L2224/48137 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2225/06562 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H04N5/4401 , H04N21/426 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A packaged semiconductor includes inner bond fingers, at least first and second semiconductor dies, and an interposer. The packaged semiconductor further includes wiring between the first and second semiconductor dies and the inner bond fingers, wiring between the interposer and the inner bond fingers, and wiring between the interposer and the first and second semiconductor dies. The wiring between the interposer and the first and second semiconductor dies thereby reduces the count of inner bond fingers needed for the wiring between the first and second semiconductor dies and the inner bond fingers. The interposer further provides indirect access to the inner bond fingers when the inner bond fingers are inaccessible by the first and second semiconductor dies.
摘要翻译： 封装半导体包括内键指，至少第一和第二半导体管芯，以及插入件。 封装半导体还包括第一和第二半导体管芯与内部接合点之间的布线，插入件与内部接合指状物之间的布线以及插入件与第一和第二半导体管芯之间的布线。 插入器与第一和第二半导体管芯之间的布线因此减少了第一和第二半导体管芯与内部接合点之间的布线所需的内部接合指的数量。 当内键指不能被第一和第二半导体管芯访问时，插入件进一步提供对内部键合指的间接访问。
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公开(公告)号：US20080258291A1
公开(公告)日：2008-10-23
申请号：US12105235
申请日：2008-04-17
申请人： Chenglin Liu , Shiann-Ming Liou , Albert Wu
发明人： Chenglin Liu , Shiann-Ming Liou , Albert Wu
IPC分类号： H01L23/492 , H01L21/50
CPC分类号： H01L23/50 , H01L23/49531 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48111 , H01L2224/48137 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2225/06562 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H04N5/4401 , H04N21/426 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A packaged semiconductor includes inner bond fingers, at least first and second semiconductor dies, and an interposer. The packaged semiconductor further includes wiring between the first and second semiconductor dies and the inner bond fingers, wiring between the interposer and the inner bond fingers, and wiring between the interposer and the first and second semiconductor dies. The wiring between the interposer and the first and second semiconductor dies thereby reduces the count of inner bond fingers needed for the wiring between the first and second semiconductor dies and the inner bond fingers. The interposer further provides indirect access to the inner bond fingers when the inner bond fingers are inaccessible by the first and second semiconductor dies.
摘要翻译： 封装半导体包括内键指，至少第一和第二半导体管芯，以及插入件。 封装半导体还包括第一和第二半导体管芯与内部接合点之间的布线，插入件与内部接合指状物之间的布线以及插入件与第一和第二半导体管芯之间的布线。 插入器与第一和第二半导体管芯之间的布线因此减少了第一和第二半导体管芯与内部接合点之间的布线所需的内部接合指的数量。 当内键指不能被第一和第二半导体管芯访问时，插入件进一步提供对内部键合指的间接访问。
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公开(公告)号：US08030098B1
公开(公告)日：2011-10-04
申请号：US12198659
申请日：2008-08-26
申请人： Shiann-Ming Liou , Albert Wu , Huahung Kao
发明人： Shiann-Ming Liou , Albert Wu , Huahung Kao
CPC分类号： H01L24/78 , H01L22/14 , H01L22/20 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/85 , H01L25/0655 , H01L25/0657 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05556 , H01L2224/05557 , H01L2224/056 , H01L2224/05624 , H01L2224/05647 , H01L2224/32145 , H01L2224/45111 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/48453 , H01L2224/48465 , H01L2224/48505 , H01L2224/48624 , H01L2224/48647 , H01L2224/48824 , H01L2224/48847 , H01L2224/78 , H01L2224/85365 , H01L2224/8581 , H01L2225/06506 , H01L2225/0651 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/14 , H01L2924/00014 , H01L2224/05639 , H01L2224/45124 , H01L2924/013 , H01L2924/00 , H01L2924/00013 , H01L2924/00012
摘要： Apparatuses including pre-forming conductive bumps on bonding pads for probing and wire-bonding connections and methods for making the same are disclosed. A method may include providing a microelectronic die including a conductive bump formed on a bonding pad, and an insulating layer formed on at least a portion of a surface of the conductive bump, and probing the conductive bump to test the microelectronic die. Other embodiments are also described.
摘要翻译： 公开了包括用于探测和引线接合连接的接合焊盘上的预成形导电凸块的装置及其制造方法。 一种方法可以包括提供一种包括在焊盘上形成的导电凸块的微电子管芯，以及形成在导电凸块表面的至少一部分上的绝缘层，并且探测导电凸块以测试微电子管芯。 还描述了其它实施例。
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公开(公告)号：US20110186998A1
公开(公告)日：2011-08-04
申请号：US13012644
申请日：2011-01-24
申请人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
发明人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
CPC分类号： H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例提供了一种装置，包括具有第一表面的半导体衬底，与第一表面相对设置的第二表面，其中第一表面的至少一部分被凹入以形成半导体衬底的凹陷区域， 以及形成在半导体衬底的凹陷区域中以在半导体衬底的第一表面和第二表面之间提供电或热路径的一个或多个通孔以及耦合到半导体衬底的管芯，该管芯电耦合到 形成在半导体衬底的凹陷区域中的一个或多个通孔。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US08319353B1
公开(公告)日：2012-11-27
申请号：US13246979
申请日：2011-09-28
申请人： Shiann-Ming Liou , Albert Wu , Huahung Kao
发明人： Shiann-Ming Liou , Albert Wu , Huahung Kao
CPC分类号： H01L24/78 , H01L22/14 , H01L22/20 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/85 , H01L25/0655 , H01L25/0657 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05556 , H01L2224/05557 , H01L2224/056 , H01L2224/05624 , H01L2224/05647 , H01L2224/32145 , H01L2224/45111 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/48453 , H01L2224/48465 , H01L2224/48505 , H01L2224/48624 , H01L2224/48647 , H01L2224/48824 , H01L2224/48847 , H01L2224/78 , H01L2224/85365 , H01L2224/8581 , H01L2225/06506 , H01L2225/0651 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/14 , H01L2924/00014 , H01L2224/05639 , H01L2224/45124 , H01L2924/013 , H01L2924/00 , H01L2924/00013 , H01L2924/00012
摘要： Apparatuses including pre-forming conductive bumps on bonding pads for probing and wire-bonding connections and methods for making the same are disclosed. A method may include providing a microelectronic die including a conductive bump formed on a bonding pad, and an insulating layer formed on at least a portion of a surface of the conductive bump, and probing the conductive bump to test the microelectronic die. Other embodiments are also described.
摘要翻译： 公开了包括用于探测和引线接合连接的接合焊盘上的预成形导电凸块的装置及其制造方法。 一种方法可以包括提供一种包括在焊盘上形成的导电凸块的微电子管芯，以及形成在导电凸块表面的至少一部分上的绝缘层，并且探测导电凸块以测试微电子管芯。 还描述了其它实施例。
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公开(公告)号：US20110180913A1
公开(公告)日：2011-07-28
申请号：US13004397
申请日：2011-01-11
申请人： Shiann-Ming Liou , Albert Wu
发明人： Shiann-Ming Liou , Albert Wu
CPC分类号： H01L21/82 , H01L23/495 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/13021 , H01L2224/13022 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2224/81136 , H01L2224/8121 , H01L2224/81815 , H01L2224/85 , H01L2224/92247 , H01L2225/0651 , H01L2225/06513 , H01L2225/06572 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for stacking chips. A first chip may be mounted on a substrate, wherein an active surface of the first chip faces away from the substrate, and wherein the first chip includes a plurality of bump pads located on the active surface of the first chip, and a wire may bond a first bump pad of the plurality of bump pads to the substrate. An intermediate layer may be disposed on at least a portion of the active surface of the first chip, and a via within the intermediate layer may extend to a second bump pad of the plurality of bump pads. A second chip may be disposed on the intermediate layer, wherein an active surface of the second chip faces towards the substrate, and wherein the second chip includes a third bump pad (i) located on the active surface of the second chip and (ii) aligned with the via formed in the intermediate layer. A corresponding bump may be disposed on one or more of (i) the second bump pad located on the active surface of the first chip and (ii) the third bump pad located on the active surface of the second chip, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad. Other embodiments are also described and claimed.
摘要翻译： 本公开的一些实施例提供用于堆叠芯片的设备，系统和方法。 第一芯片可以安装在基板上，其中第一芯片的有源表面背离基板，并且其中第一芯片包括位于第一芯片的有效表面上的多个凸点焊盘，并且导线可以键合 所述多个凸块焊盘的第一凸块焊盘到所述基板。 中间层可以设置在第一芯片的有效表面的至少一部分上，并且中间层内的通孔可以延伸到多个凸块焊盘的第二凸点焊盘。 第二芯片可以设置在中间层上，其中第二芯片的有源表面朝向衬底，并且其中第二芯片包括位于第二芯片的有效表面上的第三凸块焊盘（i），以及（ii） 与中间层中形成的通孔对准。 相应的凸块可以设置在位于第一芯片的有效表面上的（i）第二凸块焊盘中的一个或多个上，以及（ii）位于第二芯片的有效表面上的第三凸块焊盘，并且在通孔内， 其中所述相应的凸块电连接所述第二凸块焊盘与所述第三凸块焊盘。 还描述和要求保护其他实施例。
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公开(公告)号：US20110175218A1
公开(公告)日：2011-07-21
申请号：US12973249
申请日：2010-12-20
CPC分类号： H01L23/42 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L23/60 , H01L24/11 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/1403 , H01L2224/14181 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12035 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15321 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例提供了一种方法，其包括提供包括半导体材料的半导体衬底，在半导体衬底上形成电介质层，在电介质层上形成互连层，将半导体管芯附着到半导体衬底上， 半导体管芯的有源侧到互连层，互连层以引导半导体管芯的电信号。 可以描述和/或要求保护其他实施例。
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9.发明授权公开(公告)号：US09070679B2
公开(公告)日：2015-06-30
申请号：US12942918
申请日：2010-11-09
申请人： Albert Wu , Shiann-Ming Liou , Scott Wu
发明人： Albert Wu , Shiann-Ming Liou , Scott Wu
IPC分类号： H01L21/56 , H01L23/498 , H01L23/538
CPC分类号： H01L23/49833 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L23/5389 , H01L23/562 , H01L24/17 , H01L2224/16225 , H01L2224/16227 , H01L2924/07025 , H01L2924/14 , H01L2924/15151 , H01L2924/15311 , H01L2924/1579 , H01L2924/00
摘要： Embodiments of the present disclosure provide configurations for a semiconductor package and associated methods of fabricating the semiconductor package. A method of fabricating a semiconductor package includes attaching a semiconductor die to a first substrate, attaching a second substrate to the first substrate, wherein the semiconductor die is embedded in between the first substrate and the second substrate, and forming an electrically insulative structure to substantially encapsulate the semiconductor die, wherein forming the electrically insulative structure is performed subsequent to the second substrate being attached to the first substrate. Additional embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例提供了半导体封装的配置以及制造半导体封装的相关方法。 制造半导体封装的方法包括将半导体管芯附接到第一衬底，将第二衬底附接到第一衬底，其中半导体管芯被嵌入在第一衬底和第二衬底之间，并且形成电绝缘结构，以基本上 封装半导体管芯，其中在第二衬底附接到第一衬底之后执行形成电绝缘结构。 可以描述和/或要求保护附加实施例。
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公开(公告)号：US08372692B2
公开(公告)日：2013-02-12
申请号：US13004397
申请日：2011-01-11
申请人： Shiann-Ming Liou , Albert Wu
发明人： Shiann-Ming Liou , Albert Wu
CPC分类号： H01L21/82 , H01L23/495 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/13021 , H01L2224/13022 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2224/81136 , H01L2224/8121 , H01L2224/81815 , H01L2224/85 , H01L2224/92247 , H01L2225/0651 , H01L2225/06513 , H01L2225/06572 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for stacking chips. A first chip may be mounted on a substrate, wherein an active surface of the first chip faces away from the substrate, and wherein the first chip includes a plurality of bump pads located on the active surface of the first chip, and a wire may bond a first bump pad of the plurality of bump pads to the substrate. An intermediate layer may be disposed on at least a portion of the active surface of the first chip, and a via within the intermediate layer may extend to a second bump pad of the plurality of bump pads. A second chip may be disposed on the intermediate layer, wherein an active surface of the second chip faces towards the substrate, and wherein the second chip includes a third bump pad (i) located on the active surface of the second chip and (ii) aligned with the via formed in the intermediate layer. A corresponding bump may be disposed on one or more of (i) the second bump pad located on the active surface of the first chip and (ii) the third bump pad located on the active surface of the second chip, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad. Other embodiments are also described and claimed.
摘要翻译： 本公开的一些实施例提供用于堆叠芯片的设备，系统和方法。 第一芯片可以安装在基板上，其中第一芯片的有源表面背离基板，并且其中第一芯片包括位于第一芯片的有效表面上的多个凸点焊盘，并且导线可以键合 所述多个凸块焊盘的第一凸块焊盘到所述基板。 中间层可以设置在第一芯片的有效表面的至少一部分上，并且中间层内的通孔可以延伸到多个凸块焊盘的第二凸点焊盘。 第二芯片可以设置在中间层上，其中第二芯片的有源表面朝向衬底，并且其中第二芯片包括位于第二芯片的有效表面上的第三凸块焊盘（i），以及（ii） 与中间层中形成的通孔对准。 相应的凸块可以设置在位于第一芯片的有效表面上的（i）第二凸块焊盘中的一个或多个上，以及（ii）位于第二芯片的有效表面上的第三凸块焊盘，并且在通孔内， 其中所述相应的凸块电连接所述第二凸块焊盘与所述第三凸块焊盘。 还描述和要求保护其他实施例。
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