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    DISTINCT CHIP IDENTIFIER SEQUENCE UTILIZING UNCLONABLE CHARACTERISTICS OF RESISTIVE MEMORY ON A CHIP
    1.
    发明申请
    DISTINCT CHIP IDENTIFIER SEQUENCE UTILIZING UNCLONABLE CHARACTERISTICS OF RESISTIVE MEMORY ON A CHIP 有权

    公开(公告)号：US20210314177A1

    公开(公告)日：2021-10-07

    申请号：US17223832

    申请日：2021-04-06

    Applicant: CROSSBAR, INC.

    Inventor： Sung Hyun Jo ,  Hagop Nazarian ,  Sang Nguyen ,  Zhi Li

    IPC: H04L9/32 ,  G11C13/00

    Abstract: Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

    Non-volatile memory with overwrite capability and low write amplification
    2.
    发明授权
    Non-volatile memory with overwrite capability and low write amplification 有权
    具有覆盖能力和低写入放大率的非易失性存储器

    公开(公告)号：US09576616B2

    公开(公告)日：2017-02-21

    申请号：US13952467

    申请日：2013-07-26

    Applicant: Crossbar, Inc.

    Inventor： Hagop Nazarian ,  Sang Nguyen

    IPC: G11C7/00 ,  G11C13/00

    CPC classification number: G11C7/00 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/78 ,  Y10T29/49002

    Abstract: Providing for a non-volatile memory architecture having write and overwrite capabilities providing low write amplification to a storage system is described herein. By way of example, a memory array is disclosed comprising blocks and sub-blocks of two-terminal memory cells. The two-terminal memory cells can be directly overwritten in some embodiments, facilitating a write amplification value as low as one. Furthermore, the memory array can have an input-output multiplexer configuration, reducing sneak path currents of the memory architecture during memory operations.

    Abstract translation: 本文描述了具有向存储系统提供低写入放大的写入和覆盖能力的非易失性存储器架构。 作为示例，公开了包括两端存储器单元的块和子块的存储器阵列。 在一些实施例中，可以直接覆盖两端存储单元，从而有助于低至一的写入放大值。 此外，存储器阵列可以具有输入输出多路复用器配置，从而在存储器操作期间减少存储器架构的潜行路径电流。

    State change detection for two-terminal memory
    3.
    发明授权
    State change detection for two-terminal memory 有权

    公开(公告)号：US10796751B1

    公开(公告)日：2020-10-06

    申请号：US16261696

    申请日：2019-01-30

    Applicant: Crossbar, Inc.

    Inventor： Sang Nguyen ,  Hagop Nazarian ,  Tianhong Yan

    IPC: G11C11/419 ,  G11C8/18 ,  G11C7/10 ,  G11C11/418 ,  G11C7/06 ,  G11C13/00

    Abstract: A detection circuit that can detect a two-terminal memory cell changing state. For example, in response to electrical stimuli, a memory cell will change state, e.g., to a defined higher resistance state or a defined lower resistance state. Other, techniques do not detect this state change until after the stimuli is completed and a subsequent sensing operation (e.g., read pulse) is performed. The detection circuit can detect the state change during application of the electrical stimuli that cause the state change and can do so by comparing the magnitudes or values of two particular current parameters.

    Resistive random access memory equalization and sensing
    5.
    发明授权
    Resistive random access memory equalization and sensing 有权
    电阻式随机存取存储器均衡和检测

    公开(公告)号：US08982647B2

    公开(公告)日：2015-03-17

    申请号：US13676943

    申请日：2012-11-14

    Applicant: Crossbar, Inc.

    Inventor： Hagop Nazarian ,  Sang Nguyen

    IPC: G11C7/00 ,  G11C7/12 ,  G11C11/02 ,  G11C11/22 ,  G11C11/34 ,  G11C5/12 ,  G11C11/16 ,  G11C7/06 ,  G11C13/00

    CPC classification number: G11C7/12 ,  G11C5/12 ,  G11C7/062 ,  G11C11/02 ,  G11C11/1673 ,  G11C11/2297 ,  G11C11/34 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/78 ,  Y10T29/41

    Abstract: Providing for a two-terminal memory architecture that can mitigate sneak path current in conjunction with memory operations is described herein. By way of example, a voltage mimicking mechanism can be employed to dynamically drive un-selected bitlines of the memory architecture at a voltage observed by a selected bitline. According to these aspects, changes observed by the selected bitline can be applied to the un-selected bitlines as well. This can help reduce or avoid voltage differences between the selected bitline and the un-selected bitlines, thereby reducing or avoiding sneak path currents between respective bitlines of the memory architecture. Additionally, an input/output based configuration is provided to facilitate reduced sneak path current according to additional aspects of the subject disclosure.

    Abstract translation: 本文描述了提供可以减轻潜行路径电流与存储器操作相结合的两终端存储器架构。 作为示例，可以采用电压模拟机构来以所选择的位线观察到的电压来动态地驱动存储器架构的未选定位线。 根据这些方面，所选位线观察到的变化也可以应用于未选定的位线。 这可以帮助减少或避免所选择的位线与未选择的位线之间的电压差，从而减少或避免存储架构的相应位线之间的潜行路径电流。 另外，提供了基于输入/输出的配置，以根据本发明的另外的方面来促进减少的潜行路径电流。

    HIGH OPERATING SPEED RESISTIVE RANDOM ACCESS MEMORY
    6.
    发明申请
    HIGH OPERATING SPEED RESISTIVE RANDOM ACCESS MEMORY 有权
    高操作速度随机访问存储器

    公开(公告)号：US20150009745A1

    公开(公告)日：2015-01-08

    申请号：US14383079

    申请日：2013-05-24

    Applicant: Crossbar, Inc.

    Inventor： Sang Nguyen ,  Hagop Nazarian

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C11/419 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0097 ,  G11C2013/0042 ,  G11C2013/0052 ,  G11C2213/53 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79

    Abstract: Providing for resistive random access memory (RRAM) having high read speeds is described herein. By way of example, a RRAM memory can be powered at one terminal by a bitline, and connected at another terminal to a gate of a transistor having a low gate capacitance (relative to a capacitance of the bitline). With this arrangement, a signal applied at the bitline can quickly switch the transistor gate, in response to the RRAM memory being in a conductive state. A sensing circuit configured to measure the transistor can detect a change in current, voltage, etc., of the transistor and determine a state of the RRAM memory from the measurement. Moreover, this measurement can occur very quickly due to the low capacitance of the transistor gate, greatly improving the read speed of RRAM.

    Abstract translation: 本文描述了提供具有高读速度的电阻随机存取存储器（RRAM）。 作为示例，RRAM存储器可以通过位线在一个端子供电，并且在另一个端子处连接到具有低栅极电容（相对于位线的电容）的晶体管的栅极。 利用这种布置，响应于RRAM存储器处于导通状态，施加在位线处的信号可以快速地切换晶体管栅极。 配置为测量晶体管的感测电路可以检测晶体管的电流，电压等的变化，并从测量确定RRAM存储器的状态。 此外，由于晶体管栅极的低电容，该测量可能非常快地发生，极大地提高了RRAM的读取速度。

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