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公开(公告)号：US11790999B2
公开(公告)日：2023-10-17
申请号：US17242015
申请日：2021-04-27
申请人： CROSSBAR, INC.
发明人： Jeremy Guy , Sung Hyun Jo , Hagop Nazarian , Ruchirkumar Shah , Liang Zhao
CPC分类号： G11C16/3445 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C16/16 , G11C16/26
摘要： A method for erasing a memory cell includes applying a first erase to memory cells to erase the memory cells, wherein first memory cells are in a weakly erased state in response to the first erase, and wherein second memory cells are in a normally erased state in response to the first erase, thereafter applying a first weak program to the memory cells, wherein the second memory cells enter a programmed state and the third memory cells remain in the erased state in response to the first weak program, and thereafter applying a read to the memory cells to identify the second memory cells, and applying a second erase to the second memory cells to thereby erase the second memory cells.
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2.发明申请公开(公告)号：US20230005538A1
公开(公告)日：2023-01-05
申请号：US17899356
申请日：2022-08-30
申请人： CROSSBAR, INC.
发明人： Sung Hyun Jo , Hagop Nazarian , Sang Nguyen , Jeremy Guy , Zhi Li
摘要： Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.
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3.发明授权公开(公告)号：US11430517B2
公开(公告)日：2022-08-30
申请号：US17223824
申请日：2021-04-06
申请人： CROSSBAR, INC.
发明人： Sung Hyun Jo , Hagop Nazarian , Sang Nguyen , Zhi Li
摘要： Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.
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4.发明授权公开(公告)号：US11423984B2
公开(公告)日：2022-08-23
申请号：US17223816
申请日：2021-04-06
申请人： CROSSBAR, INC.
发明人： Sung Hyun Jo , Hagop Nazarian , Sang Nguyen , Zhi Li
摘要： Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.
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5.发明申请公开(公告)号：US20210312984A1
公开(公告)日：2021-10-07
申请号：US17223817
申请日：2021-04-06
申请人： CROSSBAR, INC.
发明人： Sung Hyun Jo , Hagop Nazarian , Sang Nguyen , Jeremy Guy , Zhi Li
摘要： Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.
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6.发明申请公开(公告)号：US20210312983A1
公开(公告)日：2021-10-07
申请号：US17223816
申请日：2021-04-06
申请人： CROSSBAR, INC.
发明人： Sung Hyun Jo , Hagop Nazarian , Sang Nguyen , Zhi Li
摘要： Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.
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公开(公告)号：US10910561B1
公开(公告)日：2021-02-02
申请号：US15587560
申请日：2017-05-05
申请人： Crossbar, Inc.
摘要： Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.
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公开(公告)号：US20190272882A1
公开(公告)日：2019-09-05
申请号：US16291467
申请日：2019-03-04
申请人： Crossbar, Inc.
发明人： Jeremy Guy , Sung Hyun Jo , Hagop Nazarian , Ruchirkumar Shah , Liang Xiao
摘要： A method for erasing a memory cell includes applying a first erase to memory cells to erase the memory cells, wherein first memory cells are in a weakly erased state in response to the first erase, and wherein second memory cells are in a normally erased state in response to the first erase, thereafter applying a first weak program to the memory cells, wherein the second memory cells enter a programmed state and the third memory cells remain in the erased state in response to the first weak program, and thereafter applying a read to the memory cells to identify the second memory cells, and applying a second erase to the second memory cells to thereby erase the second memory cells.
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公开(公告)号：US09847130B1
公开(公告)日：2017-12-19
申请号：US15195458
申请日：2016-06-28
申请人： Crossbar, Inc.
发明人： Sung Hyun Jo
CPC分类号： G11C13/0097 , G11C11/16 , G11C11/1659 , G11C11/56 , G11C13/0002 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/15 , G11C2213/55 , G11C2213/71 , G11C2213/76 , G11C2213/77 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L27/249 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.
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公开(公告)号：US09793474B2
公开(公告)日：2017-10-17
申请号：US14188622
申请日：2014-02-24
申请人： Crossbar, Inc.
发明人： Xin Sun , Sung Hyun Jo , Tanmay Kumar
CPC分类号： H01L45/145 , H01L21/0245 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L27/101 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/148 , H01L45/1616 , H01L45/1675
摘要： A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first electrode structure is formed overlying the first dielectric material and a p+ polycrystalline silicon germanium material is formed overlying the first electrode structure. A p+ polycrystalline silicon material is formed overlying the first electrode structure using the polycrystalline silicon germanium material as a seed layer at a deposition temperature ranging from about 430 Degree Celsius to about 475 Degree Celsius without further anneal. The method forms a resistive switching material overlying the polycrystalline silicon material, and a second electrode structure including an active metal material overlying the resistive switching material.
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