公开(公告)号：US10211229B2

公开(公告)日：2019-02-19

申请号：US15340524

申请日：2016-11-01

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.

Inventor： Zuqiang Wang

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

Abstract: A polysilicon thin film transistor, a manufacturing method thereof, an array substrate involve display technology field, and can repair the boundary defect and the defect state in polysilicon, suppress the hot carrier effect and make the characteristics of TFTs more stable. The polysilicon thin film transistor includes a gate electrode, a source electrode, a drain electrode and an active layer, the active layer comprises at least a channel area, first doped regions, second doped regions and heavily doped regions, and the first doped regions are disposed on two sides of the channel area, the second doped regions are disposed on sides of the first doped regions away from the channel area; the heavily doped regions are disposed on sides of the second doped regions opposed to the first doped regions; and dosage of ions in the heavily doped regions lies between that in the first doped regions and that in the second doped regions.

公开(公告)号：US09748280B2

公开(公告)日：2017-08-29

申请号：US14768009

申请日：2015-01-08

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Zuqiang Wang

IPC: H01L29/786 ,  H01L27/12 ,  G02F1/1368 ,  H01L29/49 ,  H01L27/32

CPC classification number: H01L27/1244 ,  G02F1/1368 ,  G02F2001/13685 ,  H01L27/1222 ,  H01L27/1274 ,  H01L27/3262 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/78675

Abstract: The present invention provides a thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device. The thin film transistor comprises a gate, a source, a drain, a gate insulation layer, an active layer, a passivation layer, a first electrode connection line and a second electrode connection line. The gate, the source and the drain are provided in the same layer and comprise the same material. The gate insulation layer is provided above the gate, the active layer is provided above the gate insulation layer, and a pattern of the gate insulation layer, a pattern of the gate and a pattern of the active layer coincide with each other. The passivation layer covers the source, the drain and the active layer, and the passivation layer has a first via hole corresponding to a position of the source, a second via hole corresponding to a position of the drain, and a third via hole and a fourth via hole corresponding to a position of the active layer provided therein. The first electrode connection line connects the source with the active layer through the first via hole and the third via hole, and the second electrode connection line connects the drain with the active layer through the second via hole and the fourth via hole.

公开(公告)号：US09269820B2

公开(公告)日：2016-02-23

申请号：US14348699

申请日：2013-11-11

Applicant: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang Wang

IPC: H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L21/306 ,  H01L21/308 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/78672 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02642 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3083 ,  H01L27/1277 ,  H01L27/1281 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/16 ,  H01L29/6675

Abstract: A manufacturing method of a polysilicon layer and a manufacturing method of a polysilicon thin film transistor. The manufacturing method of the polysilicon layer includes: providing a substrate; forming a barrier layer and a buffer layer on the substrate; disposing a plurality of grooves in the buffer layer by a patterning process, and forming crystal seeds on the buffer layer; forming an amorphous silicon layer on the buffer layer provided with the grooves and on the crystal seeds; transferring the amorphous silicon layer into a polysilicon layer using a thermal treatment process.

Abstract translation: 多晶硅层的制造方法以及多晶硅薄膜晶体管的制造方法。 多晶硅层的制造方法包括：提供基板; 在衬底上形成阻挡层和缓冲层; 通过图案化工艺在缓冲层中设置多个槽，并在缓冲层上形成晶种; 在设置有凹槽的缓冲层上和晶体晶种上形成非晶硅层; 使用热处理工艺将非晶硅层转移到多晶硅层中。

公开(公告)号：US10036906B2

公开(公告)日：2018-07-31

申请号：US15322549

申请日：2016-04-15

Applicant: Boe Technology Group Co., Ltd.

Inventor： Zuqiang Wang ,  Guang Li ,  Liang Sun ,  Xiaoyong Lu

IPC: G02F1/13 ,  G02F1/1362 ,  G02F1/1333 ,  H01L27/32 ,  G01R31/28 ,  G02F1/1368

CPC classification number: G02F1/1309 ,  G01R31/2825 ,  G02F1/133345 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136254 ,  G02F2001/136295 ,  G09G3/006 ,  G09G3/3208 ,  G09G2300/0417 ,  H01L22/34 ,  H01L27/1214 ,  H01L27/3262 ,  H01L2227/323

Abstract: A display panel which includes a display area and a peripheral area around the display area is provided. The peripheral area includes an electroluminescent layer test region, a TFT test region and a plurality of lead-out lines. The electroluminescent layer test region includes a plurality of thin film transistors having electroluminescent layers, a first test line connecting sources of the plurality of thin film transistors having electroluminescent layers, and a switch lead and a second test line connecting gates of the plurality of thin film transistors having electroluminescent layers. The TFT test region includes a plurality of thin film transistors. Each of the plurality of lead-out lines is used for connecting a source-drain metal layer of one thin film transistor in the electroluminescent layer test region and a source-drain metal layer of one thin film transistor in the TFT test region.

公开(公告)号：US09768312B2

公开(公告)日：2017-09-19

申请号：US14913048

申请日：2015-07-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hongwei Tian ,  Yanan Niu ,  Zuqiang Wang ,  Liang Sun

IPC: H01L29/786 ,  H01L21/77 ,  H01L21/02 ,  H01L21/225 ,  H01L21/30 ,  H01L21/306 ,  H01L27/12 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/78675 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/2251 ,  H01L21/3003 ,  H01L21/30604 ,  H01L21/77 ,  H01L27/1222 ,  H01L27/127 ,  H01L27/1285 ,  H01L29/1033 ,  H01L29/66757 ,  H01L29/786 ,  H01L29/78696

Abstract: Embodiments of the present invention disclose a manufacturing method of a thin film transistor, a thin film transistor, an array substrate and a display device. The manufacturing method of a thin film transistor includes a step of forming an active layer, and the step of forming an active layer includes: forming a first poly-silicon layer and a second poly-silicon layer on the first poly-silicon layer separately, and adding dopant ions into the second poly-silicon layer and an upper surface layer of the first poly-silicon layer. By using the manufacturing method of a thin film transistor, defect states and unstable factors of interface in the thin film transistor can be reduced, thereby improving stability of the LTPS thin film transistor and obtaining an array substrate and a display device having more stable performance.

公开(公告)号：US20140061633A1

公开(公告)日：2014-03-06

申请号：US13880823

申请日：2012-11-12

Applicant: Chengdu Boe Optoelectronics Technology Co., Ltd. ,  Boe Technology Group Co,Ltd

Inventor： Zuqiang Wang ,  Won Seok Kim ,  Zhengping Xiong

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/02252 ,  H01L21/02172 ,  H01L21/02244 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: Embodiments of the invention provide an oxide TFT and a manufacturing method thereof. The oxide thin film transistor comprises: a substrate; a gate electrode formed on the substrate; a gate insulation layer covering the gate electrode; an oxide active layer formed on the gate insulation layer and comprising a source region, a drain region, and a channel between the source region and the drain region; an etching barrier layer entirely covering the active layer and the gate insulation layer; and a source electrode and a drain electrode formed on the etching barrier layer and respectively provided on both sides of the channel. The etching barrier layer is a metal layer. The oxide thin film transistor further comprises a channel protective layer, which is a non-conductive oxidation layer converted from the metal layer by performing an oxidation treatment on the metal layer.

Abstract translation: 本发明的实施例提供一种氧化物TFT及其制造方法。 所述氧化物薄膜晶体管包括：基板; 形成在所述基板上的栅电极; 覆盖栅电极的栅极绝缘层; 形成在所述栅极绝缘层上的氧化物有源层，包括源极区域，漏极区域和所述源极区域与所述漏极区域之间的沟道; 完全覆盖有源层和栅极绝缘层的蚀刻阻挡层; 以及形成在蚀刻阻挡层上并分别设置在沟道两侧的源电极和漏电极。 蚀刻阻挡层是金属层。 所述氧化物薄膜晶体管还包括沟道保护层，所述沟道保护层是通过对所述金属层进行氧化处理而从所述金属层转换的非导电氧化层。

公开(公告)号：US09947697B2

公开(公告)日：2018-04-17

申请号：US14769891

申请日：2014-09-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Yinan Liang ,  Zheng Liu ,  Zuqiang Wang ,  Xueyan Tian

IPC: H01L27/12 ,  H01L27/32

CPC classification number: H01L27/1288 ,  H01L27/1255 ,  H01L27/3262 ,  H01L2227/323

Abstract: The present disclosure provides a low temperature polycrystalline silicon field effect TFT array substrate and a method for producing the same and a display apparatus. The method: using a stepped photo resist process to form a polycrystalline silicon active layer and a lower polar plate of a polycrystalline silicon storage capacitor simultaneously on a substrate in one lithographic process; forming a gate insulation layer on the polycrystalline silicon active layer and the lower polar plate of the polycrystalline silicon storage capacitor; forming a metal layer on the gate insulation layer and etching the metal layer to form a gate electrode and gate lines connected with the gate electrode, a source electrode, a drain electrode and data lines connected with the source electrode and the drain electrode; forming a passivation layer, a photo resist layer and a pixel electrode layer in sequence and patterning the passivation layer, the photo resist layer and the pixel electrode layer to form patterns of an interlayer insulation layer via hole and a pixel electrode in one lithographic process; forming a pixel definition layer on the pixel electrode. The present disclosure may reduce times of lithographic processes for the low temperature polycrystalline silicon field effect TFT array substrate, improve the yield and reduce the costs.

公开(公告)号：US20180076228A1

公开(公告)日：2018-03-15

申请号：US15529963

申请日：2016-09-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang Wang ,  Yuqing Yang ,  Lujiang Huangfu

IPC: H01L27/12 ,  H01L23/00

CPC classification number: H01L27/1218 ,  H01L23/31 ,  H01L24/05 ,  H01L24/29 ,  H01L24/83 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1262 ,  H01L2224/04026 ,  H01L2224/05006 ,  H01L2924/36

Abstract: Embodiments of the present invention provides an array substrate. The array substrate includes a display region and a packaging region. The packaging region includes a plurality of functional layers. And the packaging region further includes: a plurality of through holes running through at least one of the plurality of functional layers and configured to allow a packaging adhesive to enter therein; and a groove formed above at least some of the through holes, wherein, projection areas of the at least some of the through holes onto a base substrate of the array substrate are located within a projection area of the groove onto the base substrate. Embodiments of the present invention further provides a display panel and a display apparatus including the abovementioned array substrate, and a method of manufacturing the abovementioned array substrate.

公开(公告)号：US09585195B2

公开(公告)日：2017-02-28

申请号：US14368924

申请日：2013-11-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.

Inventor： Zuqiang Wang

IPC: H05B1/02 ,  H05B3/00 ,  H01L21/324 ,  H01L21/67 ,  H01L21/677

CPC classification number: H05B3/0047 ,  H01L21/324 ,  H01L21/67115 ,  H01L21/6776

Abstract: An annealing apparatus includes: a temperature-gradient preheating unit, configured for performing a gradient-preheating process for a substrate that is to be annealed by using a gradient temperature; a high temperature heating unit, configured for performing a high temperature heating process for the preheated substrate; and a shifting device, configured for transporting the substrate from the temperature-gradient preheating unit to the high temperature heating unit when and/or after the substrate is subjected to the gradient-preheating process. The annealing apparatus adopts a gradient heating method to perform a preheating treatment for the substrate, so the annealing efficiency is increased. An annealing process that uses the annealing apparatus is further provided.

Abstract translation: 退火装置包括：温度梯度预热单元，被配置为对通过使用梯度温度进行退火的基板进行梯度预热处理; 高温加热单元，被配置为对所述预热基板进行高温加热处理; 以及移动装置，其构造成在所述基板经受所述梯度预热处理时和/或之后将所述基板从所述温度梯度预热单元传送到所述高温加热单元。 退火装置采用梯度加热方法对基板进行预热处理，从而提高退火效率。 进一步提供使用退火装置的退火处理。

公开(公告)号：US20170040464A1

公开(公告)日：2017-02-09

申请号：US14913048

申请日：2015-07-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hongwei Tian ,  Yanan Niu ,  Zuqiang Wang ,  Liang Sun

IPC: H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L21/306 ,  H01L21/225 ,  H01L29/10 ,  H01L29/66 ,  H01L21/30

CPC classification number: H01L29/78675 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/2251 ,  H01L21/3003 ,  H01L21/30604 ,  H01L21/77 ,  H01L27/1222 ,  H01L27/127 ,  H01L27/1285 ,  H01L29/1033 ,  H01L29/66757 ,  H01L29/786 ,  H01L29/78696

Abstract: Embodiments of the present invention disclose a manufacturing method of a thin film transistor, a thin film transistor, an array substrate and a display device. The manufacturing method of a thin film transistor includes a step of forming an active layer, and the step of forming an active layer includes: forming a first poly-silicon layer and a second poly-silicon layer on the first poly-silicon layer separately, and adding dopant ions into the second poly-silicon layer and an upper surface layer of the first poly-silicon layer. By using the manufacturing method of a thin film transistor, defect states and unstable factors of interface in the thin film transistor can be reduced, thereby improving stability of the LTPS thin film transistor and obtaining an array substrate and a display device having more stable performance.

Abstract translation: 本发明的实施例公开了薄膜晶体管，薄膜晶体管，阵列基板和显示装置的制造方法。 薄膜晶体管的制造方法包括形成有源层的步骤，形成有源层的步骤包括：分别在第一多晶硅层上形成第一多晶硅层和第二多晶硅层， 以及将掺杂剂离子添加到第二多晶硅层和第一多晶硅层的上表面层。 通过使用薄膜晶体管的制造方法，可以降低薄膜晶体管的缺陷状态和界面的不稳定因素，从而提高LTPS薄膜晶体管的稳定性并获得阵列基板和具有更稳定性能的显示装置。