Abstract:
The present application discloses an array substrate comprising a base substrate; and a plurality of rows of pixel units and a plurality of rows of reset signal lines on the base substrate, every two adjacent rows of pixel units share one reset signal line. Every two adjacent rows of pixel units and a reset signal line between the two adjacent rows of pixel units constitute a pixel unit group, each pixel unit group comprises a plurality of columns of pixel units. Each pixel unit comprises a reset thin film transistor, each reset thin film transistor comprises a conductive semiconductor layer on the base substrate, a first insulating layer on a side of the conductive semiconductor layer distal to the base substrate, a gate electrode on a side of the first insulating layer distal to the conductive semiconductor layer, a second insulating layer on a side of the gate electrode distal to the first insulating layer, a source/drain/metal electrode layer on a side of the second insulating layer distal to the gate electrode, and a source via, a drain via, and a metal electrode via; the conductive semiconductor layer comprises a first semiconductor electrode and a second semiconductor electrode, and the source/drain/metal electrode layer comprises a source electrode, a drain electrode, and a metal electrode. The metal electrode via is at a position corresponding to an area where the reset signal line and the second semiconductor electrode overlap in plan view of the substrate, the metal electrode via exposing part of the reset signal line and part of the second semiconductor electrode. The metal electrode within the metal electrode via is electrically connected to the reset signal line and the second semiconductor electrode, the second semiconductor electrode is electrically connected to two drain electrodes of the reset thin film transistor in two neighboring pixel units in a same column within a same pixel unit group through two corresponding drain vias. The source electrode is electrically connected to the first semiconductor electrode through the source via.
Abstract:
The present application discloses an array substrate comprising a base substrate; and a plurality of rows of pixel units and a plurality of rows of reset signal lines on the base substrate, every two adjacent rows of pixel units share one reset signal line. Every two adjacent rows of pixel units and a reset signal line between the two adjacent rows of pixel units constitute a pixel unit group, each pixel unit group comprises a plurality of columns of pixel units. Each pixel unit comprises a reset thin film transistor, each reset thin film transistor comprises a conductive semiconductor layer on the base substrate, a first insulating layer on a side of the conductive semiconductor layer distal to the base substrate, a gate electrode on a side of the first insulating layer distal to the conductive semiconductor layer, a second insulating layer on a side of the gate electrode distal to the first insulating layer, a source/drain/metal electrode layer on a side of the second insulating layer distal to the gate electrode, and a source via, a drain via, and a metal electrode via; the conductive semiconductor layer comprises a first semiconductor electrode and a second semiconductor electrode, and the source/drain/metal electrode layer comprises a source electrode, a drain electrode, and a metal electrode. The metal electrode via is at a position corresponding to an area where the reset signal line and the second semiconductor electrode overlap in plan view of the substrate, the metal electrode via exposing part of the reset signal line and part of the second semiconductor electrode. The metal electrode within the metal electrode via is electrically connected to the reset signal line and the second semiconductor electrode, the second semiconductor electrode is electrically connected to two drain electrodes of the reset thin film transistor in two neighboring pixel units in a same column within a same pixel unit group through two corresponding drain vias. The source electrode is electrically connected to the first semiconductor electrode through the source via.
Abstract:
The present disclosure provides a display array substrate, a compensation method, a display panel and a display device. The display array substrate includes at least one power line and a voltage application unit. The at least one power line is connected to pixels in at least one column within an effective display region on the display array substrate. The power application unit is arranged outside the effective display region and configured to apply power supply voltages to at least two power supply voltage input points on the at least one power line. An absolute value of a voltage difference between the at least two power supply voltage input points is less than a predetermined voltage threshold.
Abstract:
A display panel which includes a display area and a peripheral area around the display area is provided. The peripheral area includes an electroluminescent layer test region, a TFT test region and a plurality of lead-out lines. The electroluminescent layer test region includes a plurality of thin film transistors having electroluminescent layers, a first test line connecting sources of the plurality of thin film transistors having electroluminescent layers, and a switch lead and a second test line connecting gates of the plurality of thin film transistors having electroluminescent layers. The TFT test region includes a plurality of thin film transistors. Each of the plurality of lead-out lines is used for connecting a source-drain metal layer of one thin film transistor in the electroluminescent layer test region and a source-drain metal layer of one thin film transistor in the TFT test region.
Abstract:
An array substrate, a display panel and a display device are provided. The array substrate comprises: an active area, a package area and a drive circuit area, wherein the drive circuit area is located between the active area and the package area. A package metal layer is provided at the package area, and at least one groove structure is provided on a side of the package metal layer in a proximity to the drive circuit area. At least one drive unit is provided at the drive circuit area and comprises at least one element, wherein the element is provided in the groove structure.
Abstract:
The present invention belongs to the field of display technology, and particularly relates to an array substrate, a display panel and a display device. The array substrate comprises a light-emitting unit, a driving unit for driving the light-emitting unit, and a driving signal unit for providing a driving signal to the driving unit, the driving unit being provided in a central area of the array substrate, the driving signal unit being provided on at least one side of a marginal area surrounding the central area, wherein the light-emitting unit covers the driving unit and extends into the at least one side of the marginal area on which the driving signal unit is provided. The array substrate can have not only enlarged display area but also decreased bezel width, and also have improved aperture ratio of a pixel.
Abstract:
The present disclosure provides a display array substrate, a compensation method, a display panel and a display device. The display array substrate includes at least one power line and a voltage application unit. The at least one power line is connected to pixels in at least one column within an effective display region on the display array substrate. The power application unit is arranged outside the effective display region and configured to apply power supply voltages to at least two power supply voltage input points on the at least one power line. An absolute value of a voltage difference between the at least two power supply voltage input points is less than a predetermined voltage threshold.
Abstract:
A pixel driving circuit and a driving method thereof, and an array substrate are provided. The pixel driving circuit includes a data line (Data), a gate line (Gate), a first power supply line (ELVDD), a second power supply line (ELVSS), a reference signal line (ref), a light emitting device (D), a driving transistor (T7), a storage capacitor (C1), a reset unit, a data writing unit, a compensating unit and a light emitting control unit. The pixel driving circuit can compensate and remove non-uniformity in displaying caused by variances in threshold voltage among driving transistors.