公开(公告)号：US20090178275A1

公开(公告)日：2009-07-16

申请号：US12348115

申请日：2009-01-02

申请人： Bing Dang ,  Steven L. Wright

发明人： Bing Dang ,  Steven L. Wright

IPC分类号： H05K3/00

CPC分类号： H01L23/345 ,  H01L23/147 ,  H01L23/5384 ,  H01L24/81 ,  H01L24/98 ,  H01L25/0655 ,  H01L2224/16235 ,  H01L2224/81234 ,  H01L2224/81815 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  Y10T29/4913 ,  H01L2924/00

摘要： Forming a silicon carrier interposer having an integrated heater includes forming a multi-layer silicon member having a main body portion including a first surface, a second surface and an intermediate portion, and attaching first and second electronic components to the first surface of the multi-layer silicon member. A plurality of vias extend between the first surface and the second surface and are adapted to provide an interface between the first and second electronic components and a substrate. In addition, a plurality of heating elements are integrated into the main body portion of the multi-layer silicon member. The heating elements are selectively activated to create a reflow of solder to facilitate one of an attachment of one of the first and second electronic components to the multi-layer silicon member and a detachment of the one of the first and second electronic components from the multi-layer silicon member.

摘要翻译： 形成具有集成加热器的硅载体插入件包括形成具有包括第一表面，第二表面和中间部分的主体部分的多层硅元件，以及将第一和第二电子元件附接到多层硅片的第一表面， 层硅构件。 多个通孔在第一表面和第二表面之间延伸并且适于提供第一和第二电子部件与基板之间的界面。 另外，多层加热元件集成在多层硅构件的主体部分中。 加热元件被选择性地激活以产生焊料的回流，以促进第一和第二电子元件中的一个附着到多层硅元件中的一个以及第一和第二电子元件中的一个与多层硅元件的分离 层硅构件。

公开(公告)号：US20120279287A1

公开(公告)日：2012-11-08

申请号：US13101253

申请日：2011-05-05

申请人： Paul S. Andry ,  Bing Dang ,  Steven L. Wright

发明人： Paul S. Andry ,  Bing Dang ,  Steven L. Wright

IPC分类号： G01B5/28 ,  B05D5/00 ,  C23F1/00

CPC分类号： G01B5/28 ,  B81B2201/12 ,  B81C3/001 ,  B81C2201/0194 ,  G01Q40/02 ,  G01Q70/14 ,  G01Q70/16 ,  G01R1/067 ,  G01R1/06738 ,  G01R1/07378 ,  G01R3/00 ,  G03F7/00

摘要： Transferable probe tips including a metallic probe, a delamination layer covering a portion of the metallic probe, and a bonding alloy, wherein the bonding alloy contacts the metallic probe at a portion of the probe that is not covered by the delamination layer are provided herein. Also, techniques for creating a transferable probe tip are provided, including etching a handler substrate to form one or more via arrays, depositing a delamination layer in each via array, depositing one or more metals in each via array to form a probe tip structure, and depositing a bonding alloy on a portion of the probe tip structure that is not covered by the delamination layer. Additionally, techniques for transferring transferable probe tips are provided, including removing a handler substrate from a probe tip structure, and transferring the probe tip structure via flip-chip joining the probe tip structure to a target probe head substrate.

摘要翻译： 本发明提供了包括金属探针，覆盖金属探针的一部分的分层和可接合的探针尖端，以及接合合金，其中接合合金在探针的未被分层的覆盖部分处接触金属探针。 此外，提供了用于产生可转移探针尖端的技术，包括蚀刻处理器衬底以形成一个或多个通孔阵列，在每个通孔阵列中沉积分层，在每个通孔阵列中沉积一个或多个金属以形成探针尖端结构， 以及在未被分层层覆盖的探针尖端结构的一部分上沉积接合合金。 此外，提供了用于传送可转移的探针尖端的技术，包括从探针尖端结构去除处理器基底，以及通过将探针尖端结构连接到目标探针头基底的倒装芯片来传送探针尖端结构。

公开(公告)号：US09200883B2

公开(公告)日：2015-12-01

申请号：US13101253

申请日：2011-05-05

申请人： Paul S. Andry ,  Bing Dang ,  Steven L. Wright

发明人： Paul S. Andry ,  Bing Dang ,  Steven L. Wright

IPC分类号： G01N27/84 ,  G01R33/12 ,  G01R31/26 ,  H01L21/66 ,  H01L21/44 ,  G01B5/28 ,  G03F7/00 ,  G01R1/073 ,  G01R3/00 ,  G01Q70/14 ,  G01R1/067 ,  G01Q70/16 ,  G01Q40/02

CPC分类号： G01B5/28 ,  B81B2201/12 ,  B81C3/001 ,  B81C2201/0194 ,  G01Q40/02 ,  G01Q70/14 ,  G01Q70/16 ,  G01R1/067 ,  G01R1/06738 ,  G01R1/07378 ,  G01R3/00 ,  G03F7/00

摘要： Transferable probe tips including a metallic probe, a delamination layer covering a portion of the metallic probe, and a bonding alloy, wherein the bonding alloy contacts the metallic probe at a portion of the probe that is not covered by the delamination layer are provided herein. Also, techniques for creating a transferable probe tip are provided, including etching a handler substrate to form one or more via arrays, depositing a delamination layer in each via array, depositing one or more metals in each via array to form a probe tip structure, and depositing a bonding alloy on a portion of the probe tip structure that is not covered by the delamination layer. Additionally, techniques for transferring transferable probe tips are provided, including removing a handler substrate from a probe tip structure, and transferring the probe tip structure via flip-chip joining the probe tip structure to a target probe head substrate.

摘要翻译： 本发明提供了包括金属探针，覆盖金属探针的一部分的分层和可接合的探针尖端，以及接合合金，其中接合合金在未被分层的被覆层的探针的一部分处接触金属探针。 此外，提供了用于产生可转移探针尖端的技术，包括蚀刻处理器衬底以形成一个或多个通孔阵列，在每个通孔阵列中沉积分层，在每个通孔阵列中沉积一个或多个金属以形成探针尖端结构， 以及在未被分层层覆盖的探针尖端结构的一部分上沉积接合合金。 此外，提供了用于传送可转移的探针尖端的技术，包括从探针尖端结构去除处理器基底，以及通过将探针尖端结构连接到目标探针头基底的倒装芯片来传送探针尖端结构。

公开(公告)号：US07474540B1

公开(公告)日：2009-01-06

申请号：US11972388

申请日：2008-01-10

申请人： Bing Dang ,  Steven L. Wright

发明人： Bing Dang ,  Steven L. Wright

IPC分类号： H05K1/11

CPC分类号： H01L23/345 ,  H01L23/147 ,  H01L23/5384 ,  H01L24/81 ,  H01L24/98 ,  H01L25/0655 ,  H01L2224/16235 ,  H01L2224/81234 ,  H01L2224/81815 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  Y10T29/4913 ,  H01L2924/00

摘要： A silicon carrier package includes a multi-layer member having at least a first layer and a second layer. A first electronic component includes a plurality of connector members that establish a first bond electrically interconnecting the first electronic component to the multi-layer member. A second electronic component includes a plurality of connector members that establish a second bond electrically interconnecting the second electronic component to the multi-layer member. At least one heating element is integrated into one of the first and second layers of the multi-layer member. The at least one heating element is selectively activated to loosen only one of the first and second bonds to facilitate removal of only one of the first and second electronic components from the multi-layer member. The other of the first and second bonds remains intact.

摘要翻译： 硅载体封装包括具有至少第一层和第二层的多层构件。 第一电子部件包括多个连接器构件，其建立将第一电子部件电连接到多层部件的第一接合部。 第二电子部件包括多个连接器构件，其建立将第二电子部件电连接到多层部件的第二接合部。 至少一个加热元件集成到多层构件的第一层和第二层之一中。 选择性地激活至少一个加热元件以松开仅第一和第二键中的一个，以便于从多层构件中仅去除第一和第二电子部件中的仅一个。 第一和第二债券中的另一个保持不变。

公开(公告)号：US08679280B2

公开(公告)日：2014-03-25

申请号：US12788839

申请日：2010-05-27

申请人： Bing Dang ,  Matthew Farinelli ,  John Knickerbocker ,  Aparna Prabhakar ,  Robert E. Trzcinski ,  Cornelia K. Tsang

发明人： Bing Dang ,  Matthew Farinelli ,  John Knickerbocker ,  Aparna Prabhakar ,  Robert E. Trzcinski ,  Cornelia K. Tsang

IPC分类号： B32B38/10

CPC分类号： H01L21/6835 ,  B23K26/0622 ,  B23K26/0823 ,  B23K26/361 ,  B23K26/57 ,  B23K2101/40 ,  B23K2103/42 ,  B23K2103/50 ,  C09J5/00 ,  C09J2203/326 ,  C09J2205/302 ,  C09J2400/22 ,  H01L2221/68381 ,  Y10T156/1158 ,  Y10T156/1917

摘要： A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC), includes attaching the handler to the wafer using an adhesive comprising a thermoset polymer, the handler comprising a material that is transparent in a wavelength range of about 193 nanometers (nm) to about 400 nm; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer.

摘要翻译： 一种用于从晶片释放处理器的方法，所述晶片包括集成电路（IC），包括使用包含热固性聚合物的粘合剂将所述处理器附接到所述晶片，所述处理器包括在约193的波长范围内是透明的材料 纳米（nm）至约400nm; 使用激光器通过处理器烧蚀粘合剂，其中基于处理材料的透明度选择激光的波长; 并将处理器与晶片分离。

公开(公告)号：US08419895B2

公开(公告)日：2013-04-16

申请号：US12788843

申请日：2010-05-27

申请人： Bing Dang ,  John Knickerbocker ,  Aparna Prabhakar ,  Peter Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

发明人： Bing Dang ,  John Knickerbocker ,  Aparna Prabhakar ,  Peter Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

IPC分类号： B32B38/10

CPC分类号： H01L21/6835 ,  B23K26/361 ,  H01L2221/68381 ,  Y10T156/1111 ,  Y10T156/1158 ,  Y10T156/1917

摘要： A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC) includes attaching the handler to the wafer using an adhesive comprising a polymer; performing edge processing to remove an excess portion of the adhesive from an edge of the handler and wafer; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer. A system for releasing a handler from a wafer, the wafer comprising an IC includes a handler attached to a wafer using an adhesive comprising a polymer; an edge processing module, the edge processing module configured to remove an excess portion of the adhesive from the edge of the handler and wafer; and a laser, the laser configured to ablate the adhesive through the handler.

摘要翻译： 一种用于从晶片释放处理器的方法，包括集成电路（IC）的晶片包括使用包含聚合物的粘合剂将处理器附接到晶片; 执行边缘处理以从处理器和晶片的边缘去除多余的粘合剂部分; 使用激光器通过处理器烧蚀粘合剂，其中基于处理材料的透明度选择激光的波长; 并将处理器与晶片分离。 一种用于从晶片释放处理器的系统，包括IC的晶片包括使用包含聚合物的粘合剂附接到晶片的处理器; 边缘处理模块，所述边缘处理模块被配置为从所述处理器和晶片的边缘去除所述粘合剂的多余部分; 和激光器，激光器被配置为通过处理器消融粘合剂。

公开(公告)号：US20120326290A1

公开(公告)日：2012-12-27

申请号：US13604341

申请日：2012-09-05

申请人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

发明人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

IPC分类号： H01L23/34 ,  H01L21/50

CPC分类号： H01L27/1446 ,  G02B6/4204 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/367 ,  H01L25/16 ,  H01L27/14625 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01S5/005 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02407 ,  H01S5/02476 ,  H01S5/183 ,  H01S5/423 ,  H01L2924/014 ,  H01L2924/00

摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

摘要翻译： 公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。 硅层具有允许光通过的光通孔。 光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。 多个OE元件耦合到硅层并与布线电连通。 至少一个OE元件被定位成与用于接收光的光通孔光学对准。 载体介于电互连元件之间。 载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

公开(公告)号：US20090311849A1

公开(公告)日：2009-12-17

申请号：US12140492

申请日：2008-06-17

申请人： Paul S. Andry ,  Bing Dang ,  Matthew J. Farinelli ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Bing Dang ,  Matthew J. Farinelli ,  Cornelia K. Tsang

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2221/68381 ,  H01L2224/16 ,  H01L2924/14

摘要： Improved methods of separating integrated circuit chips fabricated on a single wafer are provided. In an embodiment, a method of separating integrated circuit chips fabricated on a wafer comprises: attaching a support to a back surface of the wafer; dicing the wafer to form individual integrated circuit chips attached to the support; attaching a carrier comprising a releasable adhesive material to a front surface of the wafer opposite from the back surface; separating the support from the back surface of the wafer; subjecting the carrier to an effective amount of heat, radiation, or both to reduce the adhesiveness of the adhesive material to allow for removal of at least one of the integrated circuit chips from the carrier; and picking up and moving at least one of the integrated circuit chips using a tool configured to handle the integrated circuit chips.

摘要翻译： 提供了分离在单个晶片上制造的集成电路芯片的改进的方法。 在一个实施例中，分离在晶片上制造的集成电路芯片的方法包括：将支撑件附接到晶片的背面; 切割晶片以形成附接到支撑件的单个集成电路芯片; 将包含可释放粘合剂材料的载体附接到所述晶片的与所述后表面相对的前表面; 将支撑体从晶片的背面分离; 使载体经受有效量的热量，辐射或两者以降低粘合剂材料的粘附性，以允许将集成电路芯片中的至少一个从载体上移除; 以及使用构造成处理集成电路芯片的工具来拾取和移动至少一个集成电路芯片。

公开(公告)号：US09273408B2

公开(公告)日：2016-03-01

申请号：US13612812

申请日：2012-09-12

申请人： Bing Dang ,  Michael A. Gaynes ,  Paul A. Lauro ,  Jae-Woong Nah

发明人： Bing Dang ,  Michael A. Gaynes ,  Paul A. Lauro ,  Jae-Woong Nah

IPC分类号： B23K1/20 ,  C25D5/02 ,  H01L21/02 ,  H01L23/00 ,  C25D7/12 ,  H05K3/34

CPC分类号： H01L24/11 ,  C25D5/022 ,  C25D7/123 ,  H01L21/02107 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/11001 ,  H01L2224/11002 ,  H01L2224/11312 ,  H01L2224/1141 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1162 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K3/3436 ,  H05K2201/10734 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01026 ,  H01L2924/00

摘要： Solder bumps are provided on round wafers through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned mask layer. Solder is injected over the pillars or BLM, filling the channels. Molten solder can be injected in cavities formed in round wafers without leakage using a carrier assembly that accommodates wafers that have been previously subjected to mask layer deposition and patterning. One such carrier assembly includes an elastomeric body portion having a round recess, the walls of the recess forming a tight seal with the round wafer. Other carrier assemblies employ adhesives applied around the peripheral edges of the wafers to ensure sealing between the carrier assemblies and wafers.

摘要翻译： 通过使用注射成型焊料在圆形晶片上提供焊料凸块。 在图案化掩模层的通道内的I / O焊盘上形成铜柱或极限极限冶金。 焊料注入柱子或BLM，填充通道。 可以使用容纳预先经过掩模层沉积和图案化的晶片的载体组件将熔融的焊料注入到圆形晶片形成的空腔中而不发生泄漏。 一个这样的载体组件包括具有圆形凹部的弹性体主体部分，凹部的壁与圆形晶片形成紧密密封。 其他载体组件使用施加在晶片的周边边缘周围的粘合剂，以确保载体组件和晶片之间的密封。

公开(公告)号：US08703274B2

公开(公告)日：2014-04-22

申请号：US12244067

申请日：2008-10-02

申请人： Russell A. Budd ,  Bing Dang ,  William S. Graham ,  Peter Alfred Gruber ,  Richard Levine ,  Da-Yuan Shih

发明人： Russell A. Budd ,  Bing Dang ,  William S. Graham ,  Peter Alfred Gruber ,  Richard Levine ,  Da-Yuan Shih

IPC分类号： B32B3/00

CPC分类号： B23K1/0016 ,  B23K1/20 ,  B23K26/364 ,  B23K2101/40 ,  H05K1/111 ,  H05K3/3457 ,  H05K2201/09381 ,  H05K2201/0969 ,  H05K2201/09745 ,  H05K2203/043 ,  Y02P70/611 ,  Y10T428/24479

摘要： A microcavity structure is provided. The structure comprises a cavity layout that enables centering of reflowed solder at each of one or more interconnect locations and protrusion of the reflowed solder sufficiently from the cavity to facilitate wetting. Techniques are also provided for producing a microcavity structure, for using injection molded solder (IMS) for micro bumping, as well as for using injection molded solder (IMS) for three-dimensional (3D) packaging.

摘要翻译： 提供微腔结构。 该结构包括空腔布局，其能够使一个或多个互连位置中的每一个处的回流焊料居中并且使回流焊料从空腔充分突出以促进润湿。 还提供了用于制造微腔结构的技术，用于使用用于微型凸起的注射成型焊料（IMS）以及用于三维（3D）封装的注射成型焊料（IMS）。