公开(公告)号：US11315943B2

公开(公告)日：2022-04-26

申请号：US16643965

申请日：2018-08-28

Applicant: Applied Materials, Inc.

Inventor： Praburam Gopalraja ,  Susmit Singha Roy ,  Abhijit Basu Mallick ,  Srinivas Gandikota

IPC: H01L21/768 ,  H01L27/11582 ,  H01L27/11556

Abstract: Methods of forming memory structures are described. A metal film is deposited in the features of a structured substrate and volumetrically expanded to form pillars. A blanket film is deposited to a height less than the height of the pillars and the blanket film is removed from the top of the pillars. The height of the pillars is reduced so that the top of the pillars are below the surface of the blanket film and the process is optionally repeated to form a structure of predetermined height. The pillars can be removed from the features after formation of the predetermined height structure to form high aspect ratio features.

公开(公告)号：US20180358260A1

公开(公告)日：2018-12-13

申请号：US16003827

申请日：2018-06-08

Applicant: Applied Materials, Inc.

Inventor： Susmit Singha Roy ,  Ziqing Duan ,  Abhijit Basu Mallick ,  Praburam Gopalraja

IPC: H01L21/768 ,  H01L21/311 ,  H01J37/32

CPC classification number: H01L21/7682 ,  H01J37/32357 ,  H01J37/32715 ,  H01L21/31122 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76888 ,  H01L21/76897 ,  H01L23/53266

Abstract: A first metallization layer comprises a set of first conductive lines that extend along a first direction on a first dielectric layer on a substrate. Pillars are formed on recessed first dielectric layers and a second dielectric layer covers the pillars. A dual damascene etch provides a contact hole through the second dielectric layer and an etch removes the pillars to form air gaps.

公开(公告)号：US11177164B2

公开(公告)日：2021-11-16

申请号：US16638820

申请日：2018-08-06

Applicant: Applied Materials, Inc.

Inventor： Susmit Singha Roy ,  Praburam Gopalraja ,  Abhijit Basu Mallick ,  Srinivas Gandikota

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321

Abstract: Processing methods to form self-aligned high aspect ratio features are described. The methods comprise depositing a metal film on a structured substrate, volumetrically expanding the metal film, depositing a second film between the expanded pillars and optionally recessing the pillars and repeating the process to form the high aspect ratio features.

公开(公告)号：US10597785B2

公开(公告)日：2020-03-24

申请号：US15703626

申请日：2017-09-13

Applicant: Applied Materials, Inc.

Inventor： Anantha K. Subramani ,  Praburam Gopalraja ,  Tza-Jing Gung ,  Hari K. Ponnekanti ,  Philip Allan Kraus

IPC: C23C14/34 ,  C23C28/02 ,  C23C14/35 ,  C23C16/44 ,  C23C14/56 ,  C23C14/02 ,  C23C14/14 ,  C23C14/50 ,  C23C16/06 ,  C23C16/40 ,  C23C16/458 ,  H01J37/32 ,  H01J37/34 ,  H01L21/02 ,  H01L21/285

Abstract: Implementations described herein generally relate to metal oxide deposition in a processing chamber. More specifically, implementations disclosed herein relate to a combined chemical vapor deposition and physical vapor deposition chamber. Utilizing a single oxide metal deposition chamber capable of performing both CVD and PVD advantageously reduces the cost of uniform semiconductor processing. Additionally, the single oxide metal deposition system reduces the time necessary to deposit semiconductor substrates and reduces the foot print required to process semiconductor substrates. In one implementation, the processing chamber includes a gas distribution plate disposed in a chamber body, one or more metal targets disposed in the chamber body, and a substrate support disposed below the gas distribution plate and the one or more targets.

公开(公告)号：US09978596B2

公开(公告)日：2018-05-22

申请号：US15377629

申请日：2016-12-13

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Uday Mitra ,  Praburam Gopalraja ,  Srinivas D. Nemani ,  Hua Chung

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816

Abstract: The present disclosure provides forming nanostructures with precision dimension control and minimum lithographic related errors for features with dimension under 14 nanometers and beyond. A self-aligned multiple spacer patterning (SAMSP) process is provided herein and the process utilizes minimum lithographic exposure process, but rather multiple deposition/etching process to incrementally reduce feature sizes formed in the mask along the manufacturing process, until a desired extreme small dimension nanostructures are formed in a mask layer.

公开(公告)号：US11798606B2

公开(公告)日：2023-10-24

申请号：US17328491

申请日：2021-05-24

Applicant: Applied Materials, Inc.

Inventor： John O. Dukovic ,  Srinivas D. Nemani ,  Ellie Y. Yieh ,  Praburam Gopalraja ,  Steven Hiloong Welch ,  Bhargav S. Citla

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

公开(公告)号：US11049537B2

公开(公告)日：2021-06-29

申请号：US16525470

申请日：2019-07-29

Applicant: Applied Materials, Inc.

Inventor： John O. Dukovic ,  Srinivas D. Nemani ,  Ellie Y. Yieh ,  Praburam Gopalraja ,  Steven Hiloong Welch ,  Bhargav S. Citla

IPC: H01L43/08 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/10

Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

公开(公告)号：US10957518B2

公开(公告)日：2021-03-23

申请号：US16828694

申请日：2020-03-24

Applicant: Applied Materials, Inc.

Inventor： Kartik Ramaswamy ,  Lawrence Wong ,  Steven Lane ,  Yang Yang ,  Srinivas D. Nemani ,  Praburam Gopalraja

IPC: H01J37/32 ,  H01H1/46

Abstract: A plasma reactor includes a processing chamber having a lower processing portion having an axis of symmetry and an array of cavities extending upwardly from the lower processing portion. A gas distributor couples plural gas sources to a plurality of gas inlets of the cavities, and the gas distributor includes a plurality of valves with each valve selectively connecting a respective gas inlet to one of the plural gas sources. Power is applied by an array of conductors that includes a respective conductor for each respective cavity with each conductor adjacent and surrounding a cavity. A power distributor couples a power source and the array of conductors, and the power distributor includes a plurality of switches with a switch for each respective conductor.

公开(公告)号：US10403542B2

公开(公告)日：2019-09-03

申请号：US16003827

申请日：2018-06-08

Applicant: Applied Materials, Inc.

Inventor： Susmit Singha Roy ,  Ziqing Duan ,  Abhijit Basu Mallick ,  Praburam Gopalraja

IPC: H01L21/768 ,  H01L21/311 ,  H01J37/32 ,  H01L23/532

Abstract: A first metallization layer comprises a set of first conductive lines that extend along a first direction on a first dielectric layer on a substrate. Pillars are formed on recessed first dielectric layers and a second dielectric layer covers the pillars. A dual damascene etch provides a contact hole through the second dielectric layer and an etch removes the pillars to form air gaps.

公开(公告)号：US20170092470A1

公开(公告)日：2017-03-30

申请号：US14867240

申请日：2015-09-28

Applicant: APPLIED MATERIALS, INC.

Inventor： Kartik Ramaswamy ,  Lawrence Wong ,  Steven Lane ,  Yang Yang ,  Srinivas D. Nemani ,  Praburam Gopalraja

IPC: H01J37/32

CPC classification number: H01J37/32449 ,  H01J37/32091 ,  H01J37/3211 ,  H01J37/32422 ,  H01J37/3244 ,  H01J2237/3323 ,  H01J2237/334

Abstract: A plasma source consisting of an array of plasma point sources that controls generation of charged particles and radicals spatially and temporally over a user defined region.