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公开(公告)号：US11664809B2
公开(公告)日：2023-05-30
申请号：US17222667
申请日：2021-04-05
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
CPC classification number: H03L7/0818 , H03L7/0807 , H03L2207/12
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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公开(公告)号：US20220091622A1
公开(公告)日：2022-03-24
申请号：US17029991
申请日：2020-09-23
Applicant: Apple Inc.
Inventor： Gokce Gurun , Sanjeev K. Maheshwari , Wenbo Liu
IPC: G05F1/575
Abstract: A voltage regulator circuit included in a computer system may include a switch device coupled between an input power supply node and a regulated power supply node. The switch device may change a value of a supply current flowing from the input power supply node and the regulated power supply node to regulate a voltage level of the regulated power supply node. A noise cancelation current may be feed forward onto a control terminal of the switch device to cancel noise on the regulated power supply node resulting from noise present on the input power supply node.
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公开(公告)号：US10277230B2
公开(公告)日：2019-04-30
申请号：US15714719
申请日：2017-09-25
Applicant: Apple Inc.
Inventor： Wenbo Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari
Abstract: Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to generate a first and second sampled data signal. In some embodiments, a phase detector circuit may be configured to compare the phases of the first and second sampled data signals. In some embodiments, a first charge pump may be configured to supply a first current to a circuit node, and a second charge pump may be configured to supply a second current to the circuit node. In some embodiments, a voltage-controlled oscillator may be configured to adjust a frequency of first and second clock signals based on a voltage of the circuit node.
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公开(公告)号：US12028077B1
公开(公告)日：2024-07-02
申请号：US18172738
申请日：2023-02-22
Applicant: Apple Inc.
Inventor： Wenbo Liu , Gokce Gurun , Ajay M. Rao , Sanjeev K. Maheshwari
Abstract: A phase detector circuit for use with a multi-level signaling communication protocol on a serial communication link is disclosed. The phase detector circuit employs multiple phase and logic circuits to detect data state changes between adjacent ones of voltage levels corresponding to different data states in the communication protocol, and generates early/late signals using the detected data state changes. The phase detector circuit statistically filters data state transitions between non-adjacent voltage levels to improve phase locking and reduce recovered clock jitter.
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公开(公告)号：US11586240B1
公开(公告)日：2023-02-21
申请号：US17867117
申请日：2022-07-18
Applicant: Apple Inc.
Inventor： Bo Sun , Brian S. Leibowitz , Jafar Savoj , Sanjeev K. Maheshwari
Abstract: Embodiments relate to a circuit implementation for controlling a delay of a clock signal. The clock delay control circuit includes a sensing circuit and a phase interpolator controlled by the sensing circuit. The sensing circuit generates a first control signal that increases when a level of a supply voltage increases, and decreases when the level of the supply voltage decreases. Moreover, the sensing circuit generates a second control signal that decreases when the level of the supply voltage increases, and increases when the level of the supply voltage decreases. The phase interpolator includes multiple paths, each having a different propagation delay. The coupling between each path and the output node of the phase interpolator is controlled by the control signals generated by the sensing circuit.
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Patent Agency Ranking
公开(公告)号：US20230412132A1
公开(公告)日：2023-12-21
申请号：US17841870
申请日：2022-06-16
Applicant: Apple Inc.
Inventor： Wenbo Liu , Shang Hsien Meng , Sanjeev K. Maheshwari
CPC classification number: H03F3/393 , H03F3/45179 , H03F1/26 , H03F2200/271 , H03F2200/171 , H03F2200/555 , H03F3/347
Abstract: Low noise voltage generation circuitry includes a voltage source, a low-pass filter with one or more filter stages, and an amplifier selectively coupled to the filter stages. Each filter stage includes a resistor and a pair of capacitors of equal capacitance. The amplifier has an input selectively coupled to an output port of the voltage generation circuitry and has an output selectively coupled to the pair of capacitors in each filter stage. During a sensing phase, the amplifier senses the voltage at the output port. During a first charging phase, the amplifier has a first polarity and charges one of the pair of capacitors in each filter stage. During a second charging phase, the amplifier has a second polarity and charges another one of the pair of capacitors in each filter stage. During a final phase, the pair of capacitors within each filter stage are shorted together to cancel out an amplifier offset while the output port instantaneously settles to the target voltage.
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公开(公告)号：US11757681B1
公开(公告)日：2023-09-12
申请号：US17934891
申请日：2022-09-23
Applicant: Apple Inc.
Inventor： Jose A. Tierno , Haiming Jin , Brian S. Leibowitz , Sanjeev K. Maheshwari , Chintan S. Thakkar
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L25/03885
Abstract: To compensate for intersymbol interference, a serial data receiver circuit included in a computer system may include an equalizer circuit that includes a digital-to-analog converter circuit. Based on previously received symbols, the equalizer circuit modifies a signal received via a communication channel or link prior to clock and data recovery. In cases when the digital-to-analog converter circuit becomes saturated, the equalizer circuit additionally uses a dither signal to modify the received signal.
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公开(公告)号：US11619959B2
公开(公告)日：2023-04-04
申请号：US17029991
申请日：2020-09-23
Applicant: Apple Inc.
Inventor： Gokce Gurun , Sanjeev K. Maheshwari , Wenbo Liu
IPC: G05F1/575
Abstract: A voltage regulator circuit included in a computer system may include a switch device coupled between an input power supply node and a regulated power supply node. The switch device may change a value of a supply current flowing from the input power supply node and the regulated power supply node to regulate a voltage level of the regulated power supply node. A noise cancelation current may be feed forward onto a control terminal of the switch device to cancel noise on the regulated power supply node resulting from noise present on the input power supply node.
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公开(公告)号：US10521391B1
公开(公告)日：2019-12-31
申请号：US16204252
申请日：2018-11-29
Applicant: Apple Inc.
Inventor： Jafar Savoj , Jose A. Tierno , Sanjeev K. Maheshwari , Brian S. Leibowitz , Pradeep R. Trivedi , Gin Yee , Emerson S. Fang
Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.
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公开(公告)号：US20190097638A1
公开(公告)日：2019-03-28
申请号：US15714719
申请日：2017-09-25
Applicant: Apple Inc.
Inventor： Wenbo Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari
Abstract: Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to generate a first and second sampled data signal. In some embodiments, a phase detector circuit may be configured to compare the phases of the first and second sampled data signals. In some embodiments, a first charge pump may be configured to supply a first current to a circuit node, and a second charge pump may be configured to supply a second current to the circuit node. In some embodiments, a voltage-controlled oscillator may be configured to adjust a frequency of first and second clock signals based on a voltage of the circuit node.
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