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公开(公告)号：US20230388162A1
公开(公告)日：2023-11-30
申请号：US17804476
申请日：2022-05-27
Applicant: Apple Inc.
Inventor： Lizhi Zhong , Vishal Varma , Yu Chen , Wenyi Jin
CPC classification number: H04L25/03267 , H04B1/10
Abstract: A receiver circuit including mechanisms for analog channel equalization and channel adaptation is disclosed. The receiver includes a front-end circuit configured to generate a filtered signal by performing filtering of an incoming signal that includes a stream of data symbols. A sample recovery circuit configured to sample an equalized signal, based on the filtered signal, to generate a plurality of recovered data symbols. A decision feedback equalization (DFE) circuit configured to generate the feedback signal based on the plurality of recovered data symbols. A logic circuit is configured to cause adjustment to one or more filters in the front-end circuit based on the plurality of recovered data symbols.
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公开(公告)号：US20210226639A1
公开(公告)日：2021-07-22
申请号：US17222667
申请日：2021-04-05
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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公开(公告)号：US10972107B2
公开(公告)日：2021-04-06
申请号：US16528518
申请日：2019-07-31
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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公开(公告)号：US20210036707A1
公开(公告)日：2021-02-04
申请号：US16528518
申请日：2019-07-31
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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公开(公告)号：US11902059B2
公开(公告)日：2024-02-13
申请号：US17804476
申请日：2022-05-27
Applicant: Apple Inc.
Inventor： Lizhi Zhong , Vishal Varma , Yu Chen , Wenyi Jin
CPC classification number: H04L25/03267 , H04B1/10
Abstract: A receiver circuit including mechanisms for analog channel equalization and channel adaptation is disclosed. The receiver includes a front-end circuit configured to generate a filtered signal by performing filtering of an incoming signal that includes a stream of data symbols. A sample recovery circuit configured to sample an equalized signal, based on the filtered signal, to generate a plurality of recovered data symbols. A decision feedback equalization (DFE) circuit configured to generate the feedback signal based on the plurality of recovered data symbols. A logic circuit is configured to cause adjustment to one or more filters in the front-end circuit based on the plurality of recovered data symbols.
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Patent Agency Ranking
公开(公告)号：US10721105B2
公开(公告)日：2020-07-21
申请号：US16241415
申请日：2019-01-07
Applicant: Apple Inc.
Inventor： Lizhi Zhong
IPC: H04L25/03
Abstract: A method and apparatus for adapting, in parallel, two operating parameters associated with an equalizer circuit is disclosed. A control circuit may be configured to initialize a first operating parameter to an initial value, and modify a second operating parameter based upon the initial value of the first parameter. In response to determining a peak amplitude of an output signal of the equalizer circuit is less than a threshold value, the control circuit may be further configured to select a new value for the first operating parameter and adapt, in response to the change in the first operating parameter, the second operating parameter based on a performance metric of the equalizer circuit.
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公开(公告)号：US20190140869A1
公开(公告)日：2019-05-09
申请号：US16241415
申请日：2019-01-07
Applicant: Apple Inc.
Inventor： Lizhi Zhong
IPC: H04L25/03
CPC classification number: H04L25/03885 , H04L25/03057 , H04L25/03178 , H04L2025/0349
Abstract: A method and apparatus for adapting, in parallel, two operating parameters associated with an equalizer circuit is disclosed. A control circuit may be configured to initialize a first operating parameter to an initial value, and modify a second operating parameter based upon the initial value of the first parameter. In response to determining a peak amplitude of an output signal of the equalizer circuit is less than a threshold value, the control circuit may be further configured to select a new value for the first operating parameter and adapt, in response to the change in the first operating parameter, the second operating parameter based on a performance metric of the equalizer circuit.
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公开(公告)号：US10177945B1
公开(公告)日：2019-01-08
申请号：US15660361
申请日：2017-07-26
Applicant: Apple Inc.
Inventor： Lizhi Zhong
IPC: H04L25/03
Abstract: A method and apparatus for adapting, in parallel, two operating parameters associated with an equalizer circuit is disclosed. A control circuit may be configured to initialize a first operating parameter to an initial value, and modify a second operating parameter based upon the initial value of the first parameter. In response to determining a peak amplitude of an output signal of the equalizer circuit is less than a threshold value, the control circuit may be further configured to select a new value for the first operating parameter and adapt, in response to the change in the first operating parameter, the second operating parameter based on a performance metric of the equalizer circuit.
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公开(公告)号：US20240179034A1
公开(公告)日：2024-05-30
申请号：US18402011
申请日：2024-01-02
Applicant: Apple Inc.
Inventor： Lizhi Zhong , Vishal Varma , Yu Chen , Wenyi Jin
CPC classification number: H04L25/03267 , H04B1/10
Abstract: A receiver circuit including mechanisms for analog channel equalization and channel adaptation is disclosed. The receiver includes a front-end circuit configured to generate a filtered signal by performing filtering of an incoming signal that includes a stream of data symbols. A sample recovery circuit configured to sample an equalized signal, based on the filtered signal, to generate a plurality of recovered data symbols. A decision feedback equalization (DFE) circuit configured to generate the feedback signal based on the plurality of recovered data symbols. A logic circuit is configured to cause adjustment to one or more filters in the front-end circuit based on the plurality of recovered data symbols.
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公开(公告)号：US11664809B2
公开(公告)日：2023-05-30
申请号：US17222667
申请日：2021-04-05
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
CPC classification number: H03L7/0818 , H03L7/0807 , H03L2207/12
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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