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公开(公告)号：US20240192761A1
公开(公告)日：2024-06-13
申请号：US18064789
申请日：2022-12-12
Applicant: Apple Inc.
Inventor： Yudong Zhang , Ming-Shuan Chen , Chen-Yuan Wen , Sanjeev K. Maheshwari
CPC classification number: G06F1/06 , H03K3/037 , H03K17/687
Abstract: A sampler circuit for use with a serial communication bus includes an amplifier circuit, an isolation circuit, and a latch circuit. During a first phase, the amplifier circuit amplifies a voltage difference between a first input signal and a second input signal received via the communication bus to generate a voltage difference on output nodes of the latch circuit. During an integration phase, the latch circuit increases the voltage difference on the output nodes. During a regeneration phase, the isolation circuit isolates the amplifier circuit from the latch circuit, which generates full-rail signals based on a voltage difference between the output nodes.
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公开(公告)号：US11664809B2
公开(公告)日：2023-05-30
申请号：US17222667
申请日：2021-04-05
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
CPC classification number: H03L7/0818 , H03L7/0807 , H03L2207/12
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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Patent Agency Ranking
公开(公告)号：US10277230B2
公开(公告)日：2019-04-30
申请号：US15714719
申请日：2017-09-25
Applicant: Apple Inc.
Inventor： Wenbo Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari
Abstract: Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to generate a first and second sampled data signal. In some embodiments, a phase detector circuit may be configured to compare the phases of the first and second sampled data signals. In some embodiments, a first charge pump may be configured to supply a first current to a circuit node, and a second charge pump may be configured to supply a second current to the circuit node. In some embodiments, a voltage-controlled oscillator may be configured to adjust a frequency of first and second clock signals based on a voltage of the circuit node.
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公开(公告)号：US20190097638A1
公开(公告)日：2019-03-28
申请号：US15714719
申请日：2017-09-25
Applicant: Apple Inc.
Inventor： Wenbo Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari
Abstract: Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to generate a first and second sampled data signal. In some embodiments, a phase detector circuit may be configured to compare the phases of the first and second sampled data signals. In some embodiments, a first charge pump may be configured to supply a first current to a circuit node, and a second charge pump may be configured to supply a second current to the circuit node. In some embodiments, a voltage-controlled oscillator may be configured to adjust a frequency of first and second clock signals based on a voltage of the circuit node.
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公开(公告)号：US20210226639A1
公开(公告)日：2021-07-22
申请号：US17222667
申请日：2021-04-05
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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公开(公告)号：US10972107B2
公开(公告)日：2021-04-06
申请号：US16528518
申请日：2019-07-31
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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公开(公告)号：US20210036707A1
公开(公告)日：2021-02-04
申请号：US16528518
申请日：2019-07-31
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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