公开(公告)号：US12021577B1

公开(公告)日：2024-06-25

申请号：US18063434

申请日：2022-12-08

Applicant: Apple Inc.

Inventor： Yudong Zhang ,  Sanjeev K. Maheshwari ,  Charles L. Wang

IPC: H04B3/02 ,  H03K17/687

CPC classification number: H04B3/02 ,  H03K17/6874

Abstract: A driver circuit for a serial communication bus employs multiple switch circuits to generate different voltage levels on a set of signal lines included in the serial communication bus. The different voltage levels correspond to different values for a set of bits to be transmitted via the serial communication bus. The driver circuit also employs a shunt circuit that couples at least two of the signals together in response to the set of bits matching a particular data pattern.

公开(公告)号：US20240195453A1

公开(公告)日：2024-06-13

申请号：US18063434

申请日：2022-12-08

Applicant: Apple Inc.

Inventor： Yudong Zhang ,  Sanjeev K. Maheshwari ,  Charles L. Wang

IPC: H04B3/02 ,  H03K17/687

CPC classification number: H04B3/02 ,  H03K17/6874

Abstract: A driver circuit for a serial communication bus employs multiple switch circuits to generate different voltage levels on a set of signal lines included in the serial communication bus. The different voltage levels correspond to different values for a set of bits to be transmitted via the serial communication bus. The driver circuit also employs a shunt circuit that couples at least two of the signals together in response to the set of bits matching a particular data pattern.

公开(公告)号：US20240192761A1

公开(公告)日：2024-06-13

申请号：US18064789

申请日：2022-12-12

Applicant: Apple Inc.

Inventor： Yudong Zhang ,  Ming-Shuan Chen ,  Chen-Yuan Wen ,  Sanjeev K. Maheshwari

IPC: G06F1/06 ,  H03K3/037

CPC classification number: G06F1/06 ,  H03K3/037 ,  H03K17/687

Abstract: A sampler circuit for use with a serial communication bus includes an amplifier circuit, an isolation circuit, and a latch circuit. During a first phase, the amplifier circuit amplifies a voltage difference between a first input signal and a second input signal received via the communication bus to generate a voltage difference on output nodes of the latch circuit. During an integration phase, the latch circuit increases the voltage difference on the output nodes. During a regeneration phase, the isolation circuit isolates the amplifier circuit from the latch circuit, which generates full-rail signals based on a voltage difference between the output nodes.