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公开(公告)号：US11063600B1
公开(公告)日：2021-07-13
申请号：US16929995
申请日：2020-07-15
Applicant: Apple Inc.
Inventor： Wenbo Liu , Wei-Ming Lee , Sanjeev K. Maheshwari
Abstract: A multi-stage clock generation circuit is disclosed. The circuit includes first and second ring oscillators. The ring oscillators include a corresponding plurality of delay elements coupled in series, with a plurality of shunt circuits in parallel with corresponding inverters. The shunt circuits include respective interpolation nodes, which are resistively coupled to input and output nodes of their corresponding inverters. The interpolation nodes of the first ring oscillator are coupled to delay element input and output nodes of the second ring oscillator. Similarly, the interpolation nodes of the second ring oscillator are coupled to delay element input and output nodes of the first ring oscillator.
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公开(公告)号：US12028077B1
公开(公告)日：2024-07-02
申请号：US18172738
申请日：2023-02-22
Applicant: Apple Inc.
Inventor： Wenbo Liu , Gokce Gurun , Ajay M. Rao , Sanjeev K. Maheshwari
Abstract: A phase detector circuit for use with a multi-level signaling communication protocol on a serial communication link is disclosed. The phase detector circuit employs multiple phase and logic circuits to detect data state changes between adjacent ones of voltage levels corresponding to different data states in the communication protocol, and generates early/late signals using the detected data state changes. The phase detector circuit statistically filters data state transitions between non-adjacent voltage levels to improve phase locking and reduce recovered clock jitter.
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公开(公告)号：US20160062430A1
公开(公告)日：2016-03-03
申请号：US14471759
申请日：2014-08-28
Applicant: Apple Inc.
Inventor： Wenbo Liu , Raman S. Thiara , Shingo Hatanaka
CPC classification number: G06F1/266 , H04L25/0286 , H04L25/03
Abstract: A wired-line transmitter may include architecture that provides control of the current profile during power-up and/or power-down of the transmitter. The current profile may include a sloped ramp up during power-up and/or a sloped ramp down during power-down. The sloped ramps of the current profile mitigate supply bouncing during power-up and/or power-down. Individual enable signals may be derived from an enable signal provided to the transmitter. These individual enable signals may be provided (or turned off) in a time delayed (e.g., staggered) manner to provide the sloped ramps for the current profile.
Abstract translation: 有线线路发射机可以包括在发射机的上电和/或掉电期间提供电流分布控制的架构。 电流分布可以包括在上电期间倾斜的斜坡上升和/或掉电期间倾斜的斜坡下降。 当前配置文件的倾斜坡道能够在上电和/或掉电期间缓解供电反弹。 可以从提供给发射机的使能信号导出单独的使能信号。 可以以时间延迟（例如交错）的方式提供（或关闭）这些单独的使能信号，以提供用于当前配置文件的倾斜斜坡。
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公开(公告)号：US11664809B2
公开(公告)日：2023-05-30
申请号：US17222667
申请日：2021-04-05
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
CPC classification number: H03L7/0818 , H03L7/0807 , H03L2207/12
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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公开(公告)号：US20220091622A1
公开(公告)日：2022-03-24
申请号：US17029991
申请日：2020-09-23
Applicant: Apple Inc.
Inventor： Gokce Gurun , Sanjeev K. Maheshwari , Wenbo Liu
IPC: G05F1/575
Abstract: A voltage regulator circuit included in a computer system may include a switch device coupled between an input power supply node and a regulated power supply node. The switch device may change a value of a supply current flowing from the input power supply node and the regulated power supply node to regulate a voltage level of the regulated power supply node. A noise cancelation current may be feed forward onto a control terminal of the switch device to cancel noise on the regulated power supply node resulting from noise present on the input power supply node.
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Patent Agency Ranking
公开(公告)号：US10277230B2
公开(公告)日：2019-04-30
申请号：US15714719
申请日：2017-09-25
Applicant: Apple Inc.
Inventor： Wenbo Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari
Abstract: Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to generate a first and second sampled data signal. In some embodiments, a phase detector circuit may be configured to compare the phases of the first and second sampled data signals. In some embodiments, a first charge pump may be configured to supply a first current to a circuit node, and a second charge pump may be configured to supply a second current to the circuit node. In some embodiments, a voltage-controlled oscillator may be configured to adjust a frequency of first and second clock signals based on a voltage of the circuit node.
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公开(公告)号：US09715262B2
公开(公告)日：2017-07-25
申请号：US14471759
申请日：2014-08-28
Applicant: Apple Inc.
Inventor： Wenbo Liu , Raman S. Thiara , Shingo Hatanaka
CPC classification number: G06F1/266 , H04L25/0286 , H04L25/03
Abstract: A wired-line transmitter may include architecture that provides control of the current profile during power-up and/or power-down of the transmitter. The current profile may include a sloped ramp up during power-up and/or a sloped ramp down during power-down. The sloped ramps of the current profile mitigate supply bouncing during power-up and/or power-down. Individual enable signals may be derived from an enable signal provided to the transmitter. These individual enable signals may be provided (or turned off) in a time delayed (e.g., staggered) manner to provide the sloped ramps for the current profile.
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公开(公告)号：US20230412132A1
公开(公告)日：2023-12-21
申请号：US17841870
申请日：2022-06-16
Applicant: Apple Inc.
Inventor： Wenbo Liu , Shang Hsien Meng , Sanjeev K. Maheshwari
CPC classification number: H03F3/393 , H03F3/45179 , H03F1/26 , H03F2200/271 , H03F2200/171 , H03F2200/555 , H03F3/347
Abstract: Low noise voltage generation circuitry includes a voltage source, a low-pass filter with one or more filter stages, and an amplifier selectively coupled to the filter stages. Each filter stage includes a resistor and a pair of capacitors of equal capacitance. The amplifier has an input selectively coupled to an output port of the voltage generation circuitry and has an output selectively coupled to the pair of capacitors in each filter stage. During a sensing phase, the amplifier senses the voltage at the output port. During a first charging phase, the amplifier has a first polarity and charges one of the pair of capacitors in each filter stage. During a second charging phase, the amplifier has a second polarity and charges another one of the pair of capacitors in each filter stage. During a final phase, the pair of capacitors within each filter stage are shorted together to cancel out an amplifier offset while the output port instantaneously settles to the target voltage.
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公开(公告)号：US11619959B2
公开(公告)日：2023-04-04
申请号：US17029991
申请日：2020-09-23
Applicant: Apple Inc.
Inventor： Gokce Gurun , Sanjeev K. Maheshwari , Wenbo Liu
IPC: G05F1/575
Abstract: A voltage regulator circuit included in a computer system may include a switch device coupled between an input power supply node and a regulated power supply node. The switch device may change a value of a supply current flowing from the input power supply node and the regulated power supply node to regulate a voltage level of the regulated power supply node. A noise cancelation current may be feed forward onto a control terminal of the switch device to cancel noise on the regulated power supply node resulting from noise present on the input power supply node.
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公开(公告)号：US20190097638A1
公开(公告)日：2019-03-28
申请号：US15714719
申请日：2017-09-25
Applicant: Apple Inc.
Inventor： Wenbo Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari
Abstract: Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to generate a first and second sampled data signal. In some embodiments, a phase detector circuit may be configured to compare the phases of the first and second sampled data signals. In some embodiments, a first charge pump may be configured to supply a first current to a circuit node, and a second charge pump may be configured to supply a second current to the circuit node. In some embodiments, a voltage-controlled oscillator may be configured to adjust a frequency of first and second clock signals based on a voltage of the circuit node.
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