公开(公告)号：US12267080B2

公开(公告)日：2025-04-01

申请号：US18664811

申请日：2024-05-15

Applicant: Apple Inc.

Inventor： Jose A. Tierno ,  Ajay M. Rao

IPC: H03L7/083 ,  H03L7/085 ,  H03L7/099

Abstract: A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit configured to generate an equalized signal, a clock generator circuit configured to generate a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit is configured to monitor a frequency of the clock signal and activate an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. In response to activation of the indication signal, the clock generator circuit is configured to set the frequency of the clock signal to a particular frequency.

公开(公告)号：US20230378962A1

公开(公告)日：2023-11-23

申请号：US17664364

申请日：2022-05-20

Applicant: Apple Inc.

Inventor： Jose A. Tierno ,  Ajay M. Rao

IPC: H03L7/083 ,  H03L7/085 ,  H03L7/099

CPC classification number: H03L7/083 ,  H03L7/085 ,  H03L7/0991

Abstract: A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit that generates an equalized signal, a clock generator circuit that generates a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit monitors a frequency of the clock signal and generates an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. The clock generator circuit uses the indication signal to adjust a frequency of the clock signal.

公开(公告)号：US20240305303A1

公开(公告)日：2024-09-12

申请号：US18664811

申请日：2024-05-15

Applicant: Apple Inc.

Inventor： Jose A. Tierno ,  Ajay M. Rao

IPC: H03L7/083 ,  H03L7/085 ,  H03L7/099

CPC classification number: H03L7/083 ,  H03L7/085 ,  H03L7/0991

Abstract: A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit configured to generate an equalized signal, a clock generator circuit configured to generate a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit is configured to monitor a frequency of the clock signal and activate an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. In response to activation of the indication signal, the clock generator circuit is configured to set the frequency of the clock signal to a particular frequency.

公开(公告)号：US12028077B1

公开(公告)日：2024-07-02

申请号：US18172738

申请日：2023-02-22

Applicant: Apple Inc.

Inventor： Wenbo Liu ,  Gokce Gurun ,  Ajay M. Rao ,  Sanjeev K. Maheshwari

IPC: H03K5/24 ,  H03K3/037 ,  H03K19/20

CPC classification number: H03K5/24 ,  H03K3/037 ,  H03K19/20

Abstract: A phase detector circuit for use with a multi-level signaling communication protocol on a serial communication link is disclosed. The phase detector circuit employs multiple phase and logic circuits to detect data state changes between adjacent ones of voltage levels corresponding to different data states in the communication protocol, and generates early/late signals using the detected data state changes. The phase detector circuit statistically filters data state transitions between non-adjacent voltage levels to improve phase locking and reduce recovered clock jitter.

公开(公告)号：US12021538B2

公开(公告)日：2024-06-25

申请号：US17664364

申请日：2022-05-20

Applicant: Apple Inc.

Inventor： Jose A. Tierno ,  Ajay M. Rao

IPC: H03L7/083 ,  H03L7/085 ,  H03L7/099

CPC classification number: H03L7/083 ,  H03L7/085 ,  H03L7/0991

Abstract: A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit that generates an equalized signal, a clock generator circuit that generates a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit monitors a frequency of the clock signal and generates an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. The clock generator circuit uses the indication signal to adjust a frequency of the clock signal.