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公开(公告)号：US12021538B2
公开(公告)日：2024-06-25
申请号：US17664364
申请日：2022-05-20
Applicant: Apple Inc.
Inventor： Jose A. Tierno , Ajay M. Rao
CPC classification number: H03L7/083 , H03L7/085 , H03L7/0991
Abstract: A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit that generates an equalized signal, a clock generator circuit that generates a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit monitors a frequency of the clock signal and generates an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. The clock generator circuit uses the indication signal to adjust a frequency of the clock signal.
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公开(公告)号：US20240305303A1
公开(公告)日：2024-09-12
申请号：US18664811
申请日：2024-05-15
Applicant: Apple Inc.
Inventor： Jose A. Tierno , Ajay M. Rao
CPC classification number: H03L7/083 , H03L7/085 , H03L7/0991
Abstract: A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit configured to generate an equalized signal, a clock generator circuit configured to generate a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit is configured to monitor a frequency of the clock signal and activate an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. In response to activation of the indication signal, the clock generator circuit is configured to set the frequency of the clock signal to a particular frequency.
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公开(公告)号：US20240283436A1
公开(公告)日：2024-08-22
申请号：US18647865
申请日：2024-04-26
Applicant: Apple Inc.
Inventor： Vishal Varma , Dhaval H. Shah , Jose A. Tierno , Sanjeev K. Maheshwari , Sumeet Gupta
CPC classification number: H03K5/082 , H04L25/062
Abstract: A serial data receiver subsystem of a computer system includes a data rate detection circuit and a receiver circuit. The data rate detection circuit is configured to detect that a communication link operates in a high-speed mode rather than in a low-speed mode by detecting that a number of transitions in a serial data stream over a reference period of time exceeds a threshold value. The date rate detection circuit is further configured to activate a data rate detection signal indicating that the communication link operates in the high-speed mode, the data rate detection signal activated in response to detection that the number of transitions in the serial data stream over the reference period of time exceeds the threshold value. The receiver circuit is configured to activate one or more of a plurality of subcircuits included in the receiver circuit in response to activation of the data rate detection signal.
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公开(公告)号：US12028075B2
公开(公告)日：2024-07-02
申请号：US17823952
申请日：2022-08-31
Applicant: Apple Inc.
Inventor： Vishal Varma , Dhaval H. Shah , Jose A. Tierno , Sanjeev K. Maheshwari , Sumeet Gupta
CPC classification number: H03K5/082 , H04L25/062
Abstract: A serial data receiver subsystem included in a computer system may include a data detection circuit, a speed detection circuit, and a receiver circuit that includes multiple subcircuits. The data detection circuit performs a comparison of a reference voltage to the magnitude of signals received via a communication link that encodes a serial data stream consisting of multiple data symbols. Using a result of the comparison, the data detection circuit may activate a signal present indicator indicating the presence of data on the communication link. Once the signal present indicator is active, the speed detection circuit checks the number of transitions to determine a rate at which data is being transmitted. In response to a determination that the rate of the data being transmitted exceeds a threshold value, the receiver circuit activates one or more of the multiple subcircuits.
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公开(公告)号：US11023403B2
公开(公告)日：2021-06-01
申请号：US16700356
申请日：2019-12-02
Applicant: Apple Inc.
Inventor： Jafar Savoj , Jose A. Tierno , Sanjeev K. Maheshwari , Brian S. Leibowitz , Pradeep R. Trivedi , Gin Yee , Emerson S. Fang
Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.
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Patent Agency Ranking
公开(公告)号：US20230387898A1
公开(公告)日：2023-11-30
申请号：US17823952
申请日：2022-08-31
Applicant: Apple Inc.
Inventor： Vishal Varma , Dhaval H. Shah , Jose A. Tierno , Sanjeev K. Maheshwari , Sumeet Gupta
CPC classification number: H03K5/082 , H04L25/062
Abstract: A serial data receiver subsystem included in a computer system may include a data detection circuit, a speed detection circuit, and a receiver circuit that includes multiple subcircuits. The data detection circuit performs a comparison a reference voltage to the magnitude of signals received via a communication link that encode a serial data stream consisting of multiple data symbols. Using a result of the comparison, the data detection circuit may activate a indicating the presence of data on the communication link. Once the is active, the speed detection circuit checks the number of transitions to determine a rate at which data is being transmitted. In response to a determination that the rate of the data being transmitted exceeds a threshold value, the receiver circuit activates one or more of the multiple subcircuits.
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公开(公告)号：US20200183874A1
公开(公告)日：2020-06-11
申请号：US16700356
申请日：2019-12-02
Applicant: Apple Inc.
Inventor： Jafar Savoj , Jose A. Tierno , Sanjeev K. Maheshwari , Brian S. Leibowitz , Pradeep R. Trivedi , Gin Yee , Emerson S. Fang
Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.
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公开(公告)号：US20240097877A1
公开(公告)日：2024-03-21
申请号：US17932991
申请日：2022-09-16
Applicant: Apple Inc.
Inventor： Jose A. Tierno , Sanjeev S. Gokhale , Sunil Bhosekar , William D. Schwarz
CPC classification number: H04L7/04 , H04L25/4917
Abstract: An encoding/decoding scheme for pulse amplitude modulation (PAM) communications systems is disclosed. In one embodiment, a transmitter unit includes an encoder circuit and a transmit circuit. The encoder circuit is configured to encode an input data word having a first number of bits into a output data word having a second number of bits. The encoder performs a comparison operation to determine if at least one pair of subsets of the second plurality of bits includes bit values that are complements of each other. The encoder is further configured to modify the second plurality of bits if none of the pairs of subsets includes a bit values that are complements of each other such that the modified second plurality of bits does include at least one pair of subsets that includes values complementary to one another.
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公开(公告)号：US20230378962A1
公开(公告)日：2023-11-23
申请号：US17664364
申请日：2022-05-20
Applicant: Apple Inc.
Inventor： Jose A. Tierno , Ajay M. Rao
CPC classification number: H03L7/083 , H03L7/085 , H03L7/0991
Abstract: A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit that generates an equalized signal, a clock generator circuit that generates a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit monitors a frequency of the clock signal and generates an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. The clock generator circuit uses the indication signal to adjust a frequency of the clock signal.
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公开(公告)号：US11757681B1
公开(公告)日：2023-09-12
申请号：US17934891
申请日：2022-09-23
Applicant: Apple Inc.
Inventor： Jose A. Tierno , Haiming Jin , Brian S. Leibowitz , Sanjeev K. Maheshwari , Chintan S. Thakkar
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L25/03885
Abstract: To compensate for intersymbol interference, a serial data receiver circuit included in a computer system may include an equalizer circuit that includes a digital-to-analog converter circuit. Based on previously received symbols, the equalizer circuit modifies a signal received via a communication channel or link prior to clock and data recovery. In cases when the digital-to-analog converter circuit becomes saturated, the equalizer circuit additionally uses a dither signal to modify the received signal.
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