公开(公告)号：US11757681B1

公开(公告)日：2023-09-12

申请号：US17934891

申请日：2022-09-23

Applicant: Apple Inc.

Inventor： Jose A. Tierno ,  Haiming Jin ,  Brian S. Leibowitz ,  Sanjeev K. Maheshwari ,  Chintan S. Thakkar

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03885

Abstract: To compensate for intersymbol interference, a serial data receiver circuit included in a computer system may include an equalizer circuit that includes a digital-to-analog converter circuit. Based on previously received symbols, the equalizer circuit modifies a signal received via a communication channel or link prior to clock and data recovery. In cases when the digital-to-analog converter circuit becomes saturated, the equalizer circuit additionally uses a dither signal to modify the received signal.

公开(公告)号：US09742386B2

公开(公告)日：2017-08-22

申请号：US14969641

申请日：2015-12-15

Applicant: Apple Inc.

Inventor： Haiming Jin

IPC: H03H11/26 ,  H03K5/15

CPC classification number: H03K5/15 ,  H03K5/1504

Abstract: Clock generation circuits including a single and multi-phase clock circuits are disclosed. A clock generation circuit is coupled to receive a first pulse on a first input and a second pulse on a second input. The first pulse may be generated responsive to a rising edge of an input clock signal, while the second pulse may be generated responsive to a falling edge of the input clock signal. Responsive to the first pulse, an output node of the clock generation circuit may be pulled high. Responsive to the second pulse, the output node may be pulled low. During those points in which neither pulse is asserted, a state element in the clock generation circuit may hold the output node to its most recent value. Using delay elements and multiple instances of the clock generation circuit and pulse generation circuits, a multi-phase clock generation circuit may be constructed.

公开(公告)号：US20170170814A1

公开(公告)日：2017-06-15

申请号：US14969641

申请日：2015-12-15

Applicant: Apple Inc.

Inventor： Haiming Jin

IPC: H03K5/15

CPC classification number: H03K5/15 ,  H03K5/1504

Abstract: Clock generation circuits including a single and multi-phase clock circuits are disclosed. A clock generation circuit is coupled to receive a first pulse on a first input and a second pulse on a second input. The first pulse may be generated responsive to a rising edge of an input clock signal, while the second pulse may be generated responsive to a falling edge of the input clock signal. Responsive to the first pulse, an output node of the clock generation circuit may be pulled high. Responsive to the second pulse, the output node may be pulled low. During those points in which neither pulse is asserted, a state element in the clock generation circuit may hold the output node to its most recent value. Using delay elements and multiple instances of the clock generation circuit and pulse generation circuits, a multi-phase clock generation circuit may be constructed.