公开(公告)号：US11960739B1

公开(公告)日：2024-04-16

申请号：US17929191

申请日：2022-09-01

申请人： Apple Inc.

发明人： Robert E. Jeter ,  Jingkui Zheng ,  David A. Knopf ,  Satish B. Dulam ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan

IPC分类号： G06F3/06 ,  G11C7/22

CPC分类号： G06F3/0632 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0673 ,  G11C7/22 ,  G11C2207/2254

摘要： The present disclosure is directed to a reference voltage calibration. An apparatus includes a memory and a memory controller including a calibration circuit configured to perform a reference voltage calibration to determine a reference voltage used to distinguish between logic values read from the memory. The reference voltage calibration comprises performing horizontal calibrations at different reference voltage values to determine a range of delay values applied to a data strobe signal at which valid data is read from the memory. The calibration includes determining scores corresponding to ones of the plurality of horizontal calibrations in which a score for a particular one of the plurality of horizontal calibrations is based on a corresponding range of delay values and a reference voltage margin. Thereafter, the calibration circuit selects a calibrated reference voltage based on the scores corresponding to ones of the plurality of horizontal calibrations.

公开(公告)号：US20240078029A1

公开(公告)日：2024-03-07

申请号：US17929212

申请日：2022-09-01

申请人： Apple Inc.

发明人： Robert E. Jeter ,  Jingkui Zheng ,  Ritesh J. Shah ,  Veera Chockalingam ,  Naveen Kumar Korada

IPC分类号： G06F3/06 ,  G11C11/4076 ,  G11C11/4096

CPC分类号： G06F3/0632 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0673 ,  G11C11/4076 ,  G11C11/4096

摘要： Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.

公开(公告)号：US11501820B2

公开(公告)日：2022-11-15

申请号：US17181979

申请日：2021-02-22

申请人： Apple Inc.

发明人： Robert E. Jeter ,  Kai Lun Hsiung ,  Rakesh L. Notani ,  Venkata Ramana Malladi ,  John H. Kelm ,  Taehyun Kim

IPC分类号： G11C11/00 ,  G11C11/4074 ,  G11C11/4096 ,  G06F3/06 ,  G11C11/4076

摘要： A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.

公开(公告)号：US20200285406A1

公开(公告)日：2020-09-10

申请号：US16293398

申请日：2019-03-05

申请人： Apple Inc.

发明人： Rakesh L. Notani ,  Robert E. Jeter ,  Suhas Kumar Suvarna Ramesh ,  Naveen Kumar Korada ,  Mohammad Rizwan ,  Alma L. Juarez Dominguez ,  John H. Kelm ,  Matthew R. Johnson

IPC分类号： G06F3/06 ,  G11C11/4063 ,  G11C7/22

摘要： Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.

公开(公告)号：US20200265881A1

公开(公告)日：2020-08-20

申请号：US16277804

申请日：2019-02-15

申请人： Apple Inc.

发明人： Robert E. Jeter ,  Rakesh L. Notani ,  Venkata R. Malladi

IPC分类号： G11C7/22

摘要： A method and apparatus for performing memory calibration with endpoint replay is disclosed. A first calibration of a data strobe signal in a memory subsystem is performed. The first calibration includes determining initial values of first and second endpoints indicative of first and second delay values, respectively, applied to the data strobe signal. A second calibration of the data strobe signal is performed around these endpoints, within a range thereof that is less than a full range there between. Based on the second calibration, the endpoints are adjusted.

公开(公告)号：US10242723B1

公开(公告)日：2019-03-26

申请号：US15846992

申请日：2017-12-19

申请人： Apple Inc.

发明人： Robert E. Jeter ,  Fabien S. Faure

IPC分类号： G11C7/22 ,  G11C7/10 ,  G06F13/42

摘要： A method and apparatus for performing a background calibration in a memory subsystem is disclosed. A memory subsystem includes a memory controller coupled to a memory. The memory controller is coupled to receive data during reads from the memory on a functional data path and a duplicate data path. The memory controller further includes calibration circuitry. During reads of data conducted during normal operation, the calibration circuit calibrates a first delay locked loop (DLL) in the duplicate data path. A second DLL, in the functional data path, may be adjusted based on the calibrations conducted in the duplicate data path.

公开(公告)号：US20180074743A1

公开(公告)日：2018-03-15

申请号：US15263833

申请日：2016-09-13

申请人： Apple Inc.

发明人： Robert E. Jeter ,  Liang Deng ,  Kai Lun Hsiung ,  Manu Gulati ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Venkata Ramana Malladi ,  Gregory S. Mathews ,  Enming Zheng ,  Fabien S. Faure

IPC分类号： G06F3/06 ,  G06F1/08

CPC分类号： G06F3/0634 ,  G06F1/08 ,  G06F1/324 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/1689 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

摘要： Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

公开(公告)号：US20180061465A1

公开(公告)日：2018-03-01

申请号：US15249962

申请日：2016-08-29

申请人： Apple Inc.

发明人： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Alma L. Juarez Dominguez

IPC分类号： G11C7/22 ,  G11C7/10

CPC分类号： G11C7/22 ,  G11C7/10 ,  G11C7/222 ,  G11C11/401 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12015

摘要： A system and method for calibrating memory using credit-based segmentation control is disclosed. A memory and a memory controller coupled thereto. The memory controller includes a calibration circuit configured to calibrate a data strobe signal conveyed to/from the memory. The calibration may be subdivided, in time, into a number of segments. The memory controller also includes a credit circuit configured to provide a condition code to the calibration circuit. The condition code may be indicative of an amount of time a request has been pending, or how many request are pending. If to the condition code indicates that a request has been pending for more than a certain amount of time, the calibration may be terminated.

公开(公告)号：US09697145B2

公开(公告)日：2017-07-04

申请号：US14738265

申请日：2015-06-12

申请人： Apple Inc.

发明人： Robert E. Jeter ,  Neeraj Parik

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F13/16 ,  G06F12/02 ,  G06F12/06 ,  G11C7/10 ,  G11C8/18 ,  G11C29/02

CPC分类号： G06F13/161 ,  G06F12/023 ,  G06F12/0646 ,  G06F2212/1044 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1072 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

摘要： In some embodiments, a memory interface system includes a memory interface circuit and a memory controller. The memory interface circuit is configured to communicate with a memory device. The memory controller is configured, in response to the memory device operating at a first frequency, to store configuration information corresponding to the memory device operating at a second frequency. The memory controller is further configured, in response to the memory device transitioning to the second frequency, to send the configuration information to the memory interface circuit. In some embodiments, storing the configuration information may result in some memory requests being provided to the memory device more quickly, as compared to a different memory interface system where the configuration information is not stored at the memory controller. Additionally, in some embodiments, storing the configuration information may result in the configuration information being transmitted to the memory interface circuit more efficiently.

公开(公告)号：US09436387B2

公开(公告)日：2016-09-06

申请号：US14461865

申请日：2014-08-18

申请人： Apple Inc.

发明人： Robert E. Jeter

IPC分类号： G06F21/00 ,  G06F3/06 ,  G06F13/362 ,  G06F13/20

CPC分类号： G06F3/0604 ,  G06F3/0622 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/20 ,  G06F13/3625 ,  G06F2207/388 ,  G11C29/023 ,  G11C29/028

摘要： A system includes memory unit having one or more storage arrays, and a memory interface unit that may be coupled between a memory controller and the memory unit. The memory interface unit may include a timing unit that may generate timing signals for controlling read and write access to the memory unit, and a control unit that may calibrate the timing unit at predetermined intervals. However, in response to an occurrence of a given predetermined interval, the memory interface unit may be configured to calibrate the timing unit using a number of partial calibration segments.

摘要翻译： 系统包括具有一个或多个存储阵列的存储器单元，以及可以耦合在存储器控制器和存储器单元之间的存储器接口单元。 存储器接口单元可以包括可以生成用于控制对存储器单元的读取和写入访问的定时信号的定时单元，以及可以以预定间隔校准定时单元的控制单元。 然而，响应于给定的预定间隔的发生，存储器接口单元可以被配置为使用多个部分校准段校准定时单元。