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公开(公告)号：US20220270664A1
公开(公告)日：2022-08-25
申请号：US17181979
申请日：2021-02-22
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Kai Lun Hsiung , Rakesh L. Notani , Venkata Ramana Malladi , John H. Kelm , Taehyun Kim
IPC: G11C11/4074 , G11C11/4096 , G11C11/4076 , G06F3/06
Abstract: A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.
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公开(公告)号：US11217285B1
公开(公告)日：2022-01-04
申请号：US16986116
申请日：2020-08-05
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Rakesh L. Notani , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan , Naveen Kumar Korada
Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.
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公开(公告)号：US11960739B1
公开(公告)日：2024-04-16
申请号：US17929191
申请日：2022-09-01
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Jingkui Zheng , David A. Knopf , Satish B. Dulam , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan
CPC classification number: G06F3/0632 , G06F3/0614 , G06F3/0658 , G06F3/0673 , G11C7/22 , G11C2207/2254
Abstract: The present disclosure is directed to a reference voltage calibration. An apparatus includes a memory and a memory controller including a calibration circuit configured to perform a reference voltage calibration to determine a reference voltage used to distinguish between logic values read from the memory. The reference voltage calibration comprises performing horizontal calibrations at different reference voltage values to determine a range of delay values applied to a data strobe signal at which valid data is read from the memory. The calibration includes determining scores corresponding to ones of the plurality of horizontal calibrations in which a score for a particular one of the plurality of horizontal calibrations is based on a corresponding range of delay values and a reference voltage margin. Thereafter, the calibration circuit selects a calibrated reference voltage based on the scores corresponding to ones of the plurality of horizontal calibrations.
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公开(公告)号：US11501820B2
公开(公告)日：2022-11-15
申请号：US17181979
申请日：2021-02-22
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Kai Lun Hsiung , Rakesh L. Notani , Venkata Ramana Malladi , John H. Kelm , Taehyun Kim
IPC: G11C11/00 , G11C11/4074 , G11C11/4096 , G06F3/06 , G11C11/4076
Abstract: A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.
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公开(公告)号：US20180074743A1
公开(公告)日：2018-03-15
申请号：US15263833
申请日：2016-09-13
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Liang Deng , Kai Lun Hsiung , Manu Gulati , Rakesh L. Notani , Sukalpa Biswas , Venkata Ramana Malladi , Gregory S. Mathews , Enming Zheng , Fabien S. Faure
CPC classification number: G06F3/0634 , G06F1/08 , G06F1/324 , G06F3/0625 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G06F3/0683 , G06F13/1689 , G06F13/4243 , Y02D10/14 , Y02D10/151
Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.
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Patent Agency Ranking
公开(公告)号：US20240211151A1
公开(公告)日：2024-06-27
申请号：US18596046
申请日：2024-03-05
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Jingkui Zheng , David A. Knopf , Satish B. Dulam , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan
CPC classification number: G06F3/0632 , G06F3/0614 , G06F3/0658 , G06F3/0673 , G11C7/22 , G11C2207/2254
Abstract: An apparatus for performing a write data strobe concurrent with a reference voltage calibration is disclosed. A memory controller circuit is configured to convey a write clock signal to a memory. The memory controller circuit includes a calibration circuit configured to send a first command to memory to initiate a calibration of the write clock signal and, after an amount of time has elapsed, receive a calibration value from the memory. The memory controller further includes a delay circuit configured to apply a delay to the write clock signal, wherein the calibration circuit is configured to complete calibration of the write clock signal by adjusting the delay applied to the write clock signal in accordance with the calibration value. The calibration circuit is further configured to perform a reference voltage calibration concurrent with the calibration of the write clock signal.
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公开(公告)号：US10175905B2
公开(公告)日：2019-01-08
申请号：US15263833
申请日：2016-09-13
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Liang Deng , Kai Lun Hsiung , Manu Gulati , Rakesh L. Notani , Sukalpa Biswas , Venkata Ramana Malladi , Gregory S. Mathews , Enming Zheng , Fabien S. Faure
Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.
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公开(公告)号：US20220189519A1
公开(公告)日：2022-06-16
申请号：US17646741
申请日：2022-01-03
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Rakesh L. Notani , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan , Naveen Kumar Korada
Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.
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公开(公告)号：US09698797B1
公开(公告)日：2017-07-04
申请号：US15210852
申请日：2016-07-14
Applicant: Apple Inc.
Inventor： Manu Gulati , Suhas Kumar Suvarna Ramesh , Venkata Ramana Malladi , Thomas H. Huang , Rakesh L. Notani , Robert E. Jeter , Kai Lun Hsiung
CPC classification number: H03L7/23
Abstract: Techniques are disclosed relating to feedback-controlled oscillators (e.g., phase-locked loops) arranged in two or more levels. In some embodiments, in a relatively higher-frequency mode, a first level feedback-controlled oscillator provides reference signals to one or more second level feedback-controlled oscillators that in turn generate output clock signals to clock sequential circuitry. In some embodiments, in a relatively lower-frequency mode, the first level feedback-controlled oscillator bypasses the second level feedback-controlled oscillators and provides output clock signals directly to sequential circuitry (without using any intervening feedback-controlled oscillators).
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公开(公告)号：US12293808B2
公开(公告)日：2025-05-06
申请号：US18455385
申请日：2023-08-24
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Rakesh L. Notani , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan , Naveen Kumar Korada
Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibration, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.
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