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    Memory error tracking and logging
    1.
    发明授权
    Memory error tracking and logging 有权

    公开(公告)号：US12253913B2

    公开(公告)日：2025-03-18

    申请号：US18438802

    申请日：2024-02-12

    Applicant: Apple Inc.

    Inventor： Farid Nemati ,  Steven R. Hutsell ,  Derek R. Kumar ,  Bernard J. Semeria ,  James Vash ,  Era K. Nangia ,  Gregory S. Mathews

    IPC: G06F11/10 ,  G06F11/07

    Abstract: Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.

    Memory request management system
    3.
    发明授权
    Memory request management system 有权

    公开(公告)号：US10783104B2

    公开(公告)日：2020-09-22

    申请号：US16595230

    申请日：2019-10-07

    Applicant: Apple Inc.

    Inventor： Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Sukulpa Biswas

    IPC: G06F13/38 ,  G06F13/364 ,  G06F13/18 ,  G06F13/16

    Abstract: A memory request management system may include a memory device and a memory controller. The memory controller may include a read queue, a write queue, an arbitration circuit, a read credit allocation circuit, and a write credit allocation circuit. The read queue and write queue may store corresponding requests from request streams. The arbitration circuit may send requests from the read queue and write queue to the memory device based on locations of addresses indicated by the requests. The read credit allocation circuit may send an indication of an available read credit to a request stream in response to a read request from the request stream being sent from the read queue to the memory device. The write credit allocation circuit may send an indication of an available write credit to a request stream in response to a write request from the request stream being stored at the write queue.

    MEMORY ACCESS SCHEDULING USING CATEGORY ARBITRATION
    4.
    发明申请
    MEMORY ACCESS SCHEDULING USING CATEGORY ARBITRATION 审中-公开

    公开(公告)号：US20200081622A1

    公开(公告)日：2020-03-12

    申请号：US16565386

    申请日：2019-09-09

    Applicant: Apple Inc.

    Inventor： Gregory S. Mathews ,  Shane J. Keil ,  Sukalpa Biswas ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijavaraj

    IPC: G06F3/06

    Abstract: A memory controller circuit coupled to a memory circuit that includes multiple banks may receive multiple access requests including a particular access request to a particular bank of the plurality of banks. The particular access request is associated with a particular virtual channel of a plurality of virtual channels. The memory controller circuit may select a given access requests of the multiple access requests based on an arbitration category value associated with a virtual channel of the given access request and modify the arbitration category value in response to selecting the given access request.

    Memory request management system
    5.
    发明授权
    Memory request management system 有权

    公开(公告)号：US10437758B1

    公开(公告)日：2019-10-08

    申请号：US16024658

    申请日：2018-06-29

    Applicant: Apple Inc.

    Inventor： Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Sukulpa Biswas

    IPC: G06F13/38 ,  G06F13/364 ,  G06F13/18 ,  G06F13/16

    Abstract: A memory request management system may include a memory device and a memory controller. The memory controller may include a read queue, a write queue, an arbitration circuit, a read credit allocation circuit, and a write credit allocation circuit. The read queue and write queue may store corresponding requests from request streams. The arbitration circuit may send requests from the read queue and write queue to the memory device based on locations of addresses indicated by the requests. The read credit allocation circuit may send an indication of an available read credit to a request stream in response to a read request from the request stream being sent from the read queue to the memory device. The write credit allocation circuit may send an indication of an available write credit to a request stream in response to a write request from the request stream being stored at the write queue.

    Decoding status flag techniques for memory circuits
    6.
    发明授权
    Decoding status flag techniques for memory circuits 有权

    公开(公告)号：US12248369B2

    公开(公告)日：2025-03-11

    申请号：US18323178

    申请日：2023-05-24

    Applicant: Apple Inc.

    Inventor： Farid Nemati ,  Steven R. Hutsell ,  Gregory S. Mathews ,  Yi Chun Chen ,  Kevin C. Wong ,  Kalpana Bansal

    IPC: G06F11/10 ,  G06F11/07

    Abstract: Techniques are disclosed relating to improving memory reliability. In some embodiments, memory circuitry includes memory cells configured to store data, interface circuitry, and on-die error correcting code (ECC) circuitry. The ECC circuitry may check read data from the memory cells for errors and correct detected correctable errors to generate corrected data. The memory circuitry may provide read data to a requesting circuit via the interface circuitry, including one or more sets of corrected data from the on-die ECC circuitry. The memory circuitry may provide a decoding status flag (DSF) via the interface circuitry, including to: set the DSF to a first value in response to no error being detected for a given set of provided read data, set the DSF to a second value in response to a correctable error that was detected and corrected by the on-die ECC circuitry to provide a given set of read data, and set the DSF to a third value in response to an uncorrectable error detected by the on-die ECC circuitry.

    Data Corruption Tracking for Memory Reliability
    7.
    发明公开
    Data Corruption Tracking for Memory Reliability 审中-公开

    公开(公告)号：US20230251930A1

    公开(公告)日：2023-08-10

    申请号：US17804932

    申请日：2022-06-01

    Applicant: Apple Inc.

    Inventor： Farid Nemati ,  Steven R. Hutsell ,  Gregory S. Mathews ,  Yi Chun Chen ,  Kevin C. Wong ,  Kalpana Bansal

    IPC: G06F11/10 ,  G06F11/07

    CPC classification number: G06F11/1064 ,  G06F11/106 ,  G06F11/076 ,  G06F11/0772

    Abstract: Techniques are disclosed relating to improving memory reliability, e.g., in the context of memory circuits with limited reliability features. In some embodiments, memory controller circuitry is configured to communicate with memory circuitry via an interface that supports link error detection. The memory controller circuitry may, based on a corruption indicator, transmit a data and parity combination for the first data block that causes the memory circuitry to detect an uncorrectable write interface error. Subsequent reads of the location may therefore cause an uncorrectable error indication. This may advantageously allow the memory controller circuitry to propagate a corruption indicator as an uncorrectable error in the memory circuit, without requiring additional tracking of the indicator by the memory circuit or memory controller, in some embodiments.

    Multi-Activation Techniques for Partial Write Operations
    8.
    发明申请
    Multi-Activation Techniques for Partial Write Operations 有权

    公开(公告)号：US20230068494A1

    公开(公告)日：2023-03-02

    申请号：US17410657

    申请日：2021-08-24

    Applicant: Apple Inc.

    Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala

    IPC: G06F3/06

    Abstract: Techniques are disclosed relating to multi-activation techniques for wire operations with multiple partial writes. In some embodiments, a memory controller is configured to access data in a memory device that supports partial writes having a first size using read-modify-write operations and non-partial writes having a second size that is greater than the first size. In some embodiments, the memory controller is configured to queue a first write operation having the second size, where the first write operation includes multiple partial writes. In some embodiments, the memory controller is configured to send separate activate signals to the memory device to activate a bank of the memory device to perform different proper subsets of the multiple partial writes. This may allow interleaving of other accesses to a memory bank and merging of writes while waiting for a current activation, in some embodiments.

    System and method for performing per-bank memory refresh
    9.
    发明授权
    System and method for performing per-bank memory refresh 有权

    公开(公告)号：US10777252B2

    公开(公告)日：2020-09-15

    申请号：US16109720

    申请日：2018-08-22

    Applicant: Apple Inc.

    Inventor： Peter Fu ,  Gregory S. Mathews ,  Kai Lun Hsuing ,  Shane J. Keil

    IPC: G06F13/00 ,  G11C11/406 ,  G06F13/16 ,  G06F13/10 ,  G06F13/12

    Abstract: A method and apparatus for performing opportunistic refreshes of memory banks is disclosed. Refresh circuitry in a memory controller performs a refresh on each bank of a multi-bank memory at least once during a given refresh interval. At the beginning of an interval, memory banks for which there are no pending transactions (e.g., reads or writes) may be refreshed. During a first portion of the interval, refresh may be skipped for memory banks for which transactions are pending. In a second portion of the interval, refreshes are performed on memory banks that have not been refreshed during the interval, which may cause some memory transactions to be delayed.

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