-
公开(公告)号：US20230325274A1
公开(公告)日：2023-10-12
申请号：US18323178
申请日：2023-05-24
Applicant: Apple Inc.
Inventor： Farid Nemati , Steven R. Hutsell , Gregory S. Mathews , Yi Chun Chen , Kevin C. Wong , Kalpana Bansal
CPC classification number: G06F11/1064 , G06F11/076 , G06F11/0772 , G06F11/106
Abstract: Techniques are disclosed relating to improving memory reliability. In some embodiments, memory circuitry includes memory cells configured to store data, interface circuitry, and on-die error correcting code (ECC) circuitry. The ECC circuitry may check read data from the memory cells for errors and correct detected correctable errors to generate corrected data. The memory circuitry may provide read data to a requesting circuit via the interface circuitry, including one or more sets of corrected data from the on-die ECC circuitry. The memory circuitry may provide a decoding status flag (DSF) via the interface circuitry, including to: set the DSF to a first value in response to no error being detected for a given set of provided read data, set the DSF to a second value in response to a correctable error that was detected and corrected by the on-die ECC circuitry to provide a given set of read data, and set the DSF to a third value in response to an uncorrectable error detected by the on-die ECC circuitry.
-
公开(公告)号：US11829242B2
公开(公告)日：2023-11-28
申请号：US17804932
申请日：2022-06-01
Applicant: Apple Inc.
Inventor： Farid Nemati , Steven R. Hutsell , Gregory S. Mathews , Yi Chun Chen , Kevin C. Wong , Kalpana Bansal
CPC classification number: G06F11/1064 , G06F11/076 , G06F11/0772 , G06F11/106
Abstract: Techniques are disclosed relating to improving memory reliability, e.g., in the context of memory circuits with limited reliability features. In some embodiments, memory controller circuitry is configured to communicate with memory circuitry via an interface that supports link error detection. The memory controller circuitry may, based on a corruption indicator, transmit a data and parity combination for the first data block that causes the memory circuitry to detect an uncorrectable write interface error. Subsequent reads of the location may therefore cause an uncorrectable error indication. This may advantageously allow the memory controller circuitry to propagate a corruption indicator as an uncorrectable error in the memory circuit, without requiring additional tracking of the indicator by the memory circuit or memory controller, in some embodiments.
-
Patent Agency Ranking
公开(公告)号：US11720520B2
公开(公告)日：2023-08-08
申请号：US17535590
申请日：2021-11-25
Applicant: APPLE INC.
Inventor： John H Kelm , Alexei E Kosut , Yi Chun Chen
CPC classification number: G06F13/4295 , G06F1/12 , G06F2213/0042
Abstract: An apparatus includes components, a distributed timebase circuit, an interface and a Time Synchronization Circuit (TSC). The timebase circuit is configured to provide local timebases in physical proximity to the components, and synchronize the local timebases to a global timebase so as to provide a consistent time measurement. The interface is configured to be coupled to one or more devices. Transmissions on the interface are logically divided into a plurality of frames. Time on the interface is defined based on a frame number identifying a particular frame. The TSC is configured to capture a first timestamp based on the frame number corresponding to a point in time on the interface, and to concurrently capture a second timestamp based on a local timebase corresponding to the point in time, wherein the first timestamp and the second timestamp correlate time on the interface to the consistent time measurement.
-
公开(公告)号：US20230082266A1
公开(公告)日：2023-03-16
申请号：US17535590
申请日：2021-11-25
Applicant: APPLE INC.
Inventor： John H Kelm , Alexei E Kosut , Yi Chun Chen
Abstract: An apparatus includes components, a distributed timebase circuit, an interface and a Time Synchronization Circuit (TSC). The timebase circuit is configured to provide local timebases in physical proximity to the components, and synchronize the local timebases to a global timebase so as to provide a consistent time measurement. The interface is configured to be coupled to one or more devices. Transmissions on the interface are logically divided into a plurality of frames. Time on the interface is defined based on a frame number identifying a particular frame. The TSC is configured to capture a first timestamp based on the frame number corresponding to a point in time on the interface, and to concurrently capture a second timestamp based on a local timebase corresponding to the point in time, wherein the first timestamp and the second timestamp correlate time on the interface to the consistent time measurement.
-
公开(公告)号：US12248369B2
公开(公告)日：2025-03-11
申请号：US18323178
申请日：2023-05-24
Applicant: Apple Inc.
Inventor： Farid Nemati , Steven R. Hutsell , Gregory S. Mathews , Yi Chun Chen , Kevin C. Wong , Kalpana Bansal
Abstract: Techniques are disclosed relating to improving memory reliability. In some embodiments, memory circuitry includes memory cells configured to store data, interface circuitry, and on-die error correcting code (ECC) circuitry. The ECC circuitry may check read data from the memory cells for errors and correct detected correctable errors to generate corrected data. The memory circuitry may provide read data to a requesting circuit via the interface circuitry, including one or more sets of corrected data from the on-die ECC circuitry. The memory circuitry may provide a decoding status flag (DSF) via the interface circuitry, including to: set the DSF to a first value in response to no error being detected for a given set of provided read data, set the DSF to a second value in response to a correctable error that was detected and corrected by the on-die ECC circuitry to provide a given set of read data, and set the DSF to a third value in response to an uncorrectable error detected by the on-die ECC circuitry.
-
公开(公告)号：US20230325344A1
公开(公告)日：2023-10-12
申请号：US18334394
申请日：2023-06-14
Applicant: APPLE INC.
Inventor： John H. Kelm , Alexei E. Kosut , Yi Chun Chen
CPC classification number: G06F13/4295 , G06F1/12 , G06F2213/0042
Abstract: An apparatus includes components, a distributed timebase circuit, an interface and a Time Synchronization Circuit (TSC). The timebase circuit is configured to provide local timebases in physical proximity to the components, and synchronize the local timebases to a global timebase so as to provide a consistent time measurement. The interface is configured to be coupled to one or more devices. Transmissions on the interface are logically divided into a plurality of frames. Time on the interface is defined based on a frame number identifying a particular frame. The TSC is configured to capture a first timestamp based on the frame number corresponding to a point in time on the interface, and to concurrently capture a second timestamp based on a local timebase corresponding to the point in time, wherein the first timestamp and the second timestamp correlate time on the interface to the consistent time measurement.
-
公开(公告)号：US20230251930A1
公开(公告)日：2023-08-10
申请号：US17804932
申请日：2022-06-01
Applicant: Apple Inc.
Inventor： Farid Nemati , Steven R. Hutsell , Gregory S. Mathews , Yi Chun Chen , Kevin C. Wong , Kalpana Bansal
CPC classification number: G06F11/1064 , G06F11/106 , G06F11/076 , G06F11/0772
Abstract: Techniques are disclosed relating to improving memory reliability, e.g., in the context of memory circuits with limited reliability features. In some embodiments, memory controller circuitry is configured to communicate with memory circuitry via an interface that supports link error detection. The memory controller circuitry may, based on a corruption indicator, transmit a data and parity combination for the first data block that causes the memory circuitry to detect an uncorrectable write interface error. Subsequent reads of the location may therefore cause an uncorrectable error indication. This may advantageously allow the memory controller circuitry to propagate a corruption indicator as an uncorrectable error in the memory circuit, without requiring additional tracking of the indicator by the memory circuit or memory controller, in some embodiments.
-
-
-
-
-
-
Search Results
7
records
(took 0.064 seconds)
