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    Datalogging Circuit Triggered by a Watchdog Timer
    1.
    发明公开
    Datalogging Circuit Triggered by a Watchdog Timer 审中-公开

    公开(公告)号：US20240118958A1

    公开(公告)日：2024-04-11

    申请号：US18529472

    申请日：2023-12-05

    Applicant: Apple Inc.

    Inventor： John H. Kelm ,  Richard H. Larson ,  Charles J. Fleckenstein

    IPC: G06F11/07

    CPC classification number: G06F11/0757

    Abstract: An apparatus includes a memory circuit, and an integrated circuit formed on a single semiconductor substrate and coupled to the memory circuit. The integrated circuit includes a watchdog timer, a plurality of functional circuits coupled together via a communication fabric, and a system management circuit coupled to the watchdog timer and to a subset of the functional circuits via respective dedicated point-to-point interfaces. A given functional circuit may be configured to repeatedly reset the watchdog timer before the watchdog timer expires. The system management circuit may be configured, in response to an expiration of the watchdog timer, to access information in the subset of the functional circuits via the respective point-to-point interfaces. The system management circuit may be further configured to store the accessed information in the memory circuit.

    Remapping techniques for message signaled interrupts
    2.
    发明授权
    Remapping techniques for message signaled interrupts 有权

    公开(公告)号：US11550745B1

    公开(公告)日：2023-01-10

    申请号：US17480449

    申请日：2021-09-21

    Applicant: Apple Inc.

    Inventor： John H. Kelm

    IPC: G06F13/24 ,  G06F12/1045 ,  G06F13/16

    Abstract: Techniques are disclosed relating to address mapping for message signaled interrupts. In some embodiments, an apparatus includes interrupt control circuitry configured to process, from multiple client circuits, message signaled interrupts that include addresses in an interrupt controller address space. First and second interface controller circuitry may control respective peripheral interfaces for multiple devices. Remap control circuitry may be configured to access a first table based on at least a portion of virtual addresses of a first message signaled interrupt from the first interface controller circuit and generate a first address in the interrupt controller address space based on an accessed entry in the first table and access a second table based on at least a portion of virtual addresses of a second message signaled interrupt from the second interface controller circuit and generate a second address in the interrupt controller address space based on an accessed entry in the second table.

    Cache quota control
    4.
    发明授权
    Cache quota control 有权

    公开(公告)号：US11914521B1

    公开(公告)日：2024-02-27

    申请号：US17809822

    申请日：2022-06-29

    Applicant: Apple Inc.

    Inventor： Wolfgang H. Klingauf ,  Muhammad Umer Amjad ,  Connie W. Cheung ,  Yueh-Ta Wu ,  Muditha Kanchana ,  John H. Kelm

    IPC: G06F12/0895 ,  G06F12/0837 ,  G06F12/0873

    CPC classification number: G06F12/0895 ,  G06F12/0837 ,  G06F12/0873

    Abstract: A mechanism for cache quota control is disclosed. A cache memory is configured to receive access requests from a plurality of agents, wherein a given request from a given agent of the plurality of agents specifies an identification value associated with the given agent of the plurality of agents. A cache controller is coupled to the cache memory, and is configured to store indications of current allocations of the cache memory to individual ones of the plurality of agents. The cache controller is further configured to track requests to the cache memory based on identification values specified in the requests and determine whether to update allocations of the cache memory to the individual ones of the plurality of agents based on the tracked requests.

    Selective Reference Voltage Calibration in Memory Subsystem
    7.
    发明申请
    Selective Reference Voltage Calibration in Memory Subsystem 有权

    公开(公告)号：US20220270664A1

    公开(公告)日：2022-08-25

    申请号：US17181979

    申请日：2021-02-22

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Kai Lun Hsiung ,  Rakesh L. Notani ,  Venkata Ramana Malladi ,  John H. Kelm ,  Taehyun Kim

    IPC: G11C11/4074 ,  G11C11/4096 ,  G11C11/4076 ,  G06F3/06

    Abstract: A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.

    Universal serial bus time synchronization
    8.
    发明公开
    Universal serial bus time synchronization 审中-公开

    公开(公告)号：US20230325344A1

    公开(公告)日：2023-10-12

    申请号：US18334394

    申请日：2023-06-14

    Applicant: APPLE INC.

    Inventor： John H. Kelm ,  Alexei E. Kosut ,  Yi Chun Chen

    IPC: G06F13/42 ,  G06F1/12

    CPC classification number: G06F13/4295 ,  G06F1/12 ,  G06F2213/0042

    Abstract: An apparatus includes components, a distributed timebase circuit, an interface and a Time Synchronization Circuit (TSC). The timebase circuit is configured to provide local timebases in physical proximity to the components, and synchronize the local timebases to a global timebase so as to provide a consistent time measurement. The interface is configured to be coupled to one or more devices. Transmissions on the interface are logically divided into a plurality of frames. Time on the interface is defined based on a frame number identifying a particular frame. The TSC is configured to capture a first timestamp based on the frame number corresponding to a point in time on the interface, and to concurrently capture a second timestamp based on a local timebase corresponding to the point in time, wherein the first timestamp and the second timestamp correlate time on the interface to the consistent time measurement.

    Selective reference voltage calibration in memory subsystem
    9.
    发明授权
    Selective reference voltage calibration in memory subsystem 有权

    公开(公告)号：US11501820B2

    公开(公告)日：2022-11-15

    申请号：US17181979

    申请日：2021-02-22

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Kai Lun Hsiung ,  Rakesh L. Notani ,  Venkata Ramana Malladi ,  John H. Kelm ,  Taehyun Kim

    IPC: G11C11/00 ,  G11C11/4074 ,  G11C11/4096 ,  G06F3/06 ,  G11C11/4076

    Abstract: A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.

    DSB Operation with Excluded Region
    10.
    发明申请
    DSB Operation with Excluded Region 有权

    公开(公告)号：US20220083338A1

    公开(公告)日：2022-03-17

    申请号：US17469504

    申请日：2021-09-08

    Applicant: Apple Inc.

    Inventor： Jeff Gonion ,  John H. Kelm ,  James Vash ,  Pradeep Kanapathipillai ,  Mridul Agarwal ,  Gideon N. Levinsky ,  Richard F. Russo ,  Christopher M. Tsay

    IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/02

    Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.

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