公开(公告)号：US11501820B2

公开(公告)日：2022-11-15

申请号：US17181979

申请日：2021-02-22

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Kai Lun Hsiung ,  Rakesh L. Notani ,  Venkata Ramana Malladi ,  John H. Kelm ,  Taehyun Kim

IPC: G11C11/00 ,  G11C11/4074 ,  G11C11/4096 ,  G06F3/06 ,  G11C11/4076

Abstract: A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.

公开(公告)号：US20220270664A1

公开(公告)日：2022-08-25

申请号：US17181979

申请日：2021-02-22

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Kai Lun Hsiung ,  Rakesh L. Notani ,  Venkata Ramana Malladi ,  John H. Kelm ,  Taehyun Kim

IPC: G11C11/4074 ,  G11C11/4096 ,  G11C11/4076 ,  G06F3/06

Abstract: A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.