公开(公告)号：US09082118B2

公开(公告)日：2015-07-14

申请号：US13944462

申请日：2013-07-17

Applicant: Apple Inc.

Inventor： Gurjeet S. Saund ,  Munetoshi Fukami ,  Kevin C. Wong

IPC: G06F17/50 ,  G06Q20/38 ,  G06Q20/24

CPC classification number: G06Q20/38 ,  G06F17/5045 ,  G06F17/505 ,  G06Q20/24

Abstract: Embodiments of a local interface unit are disclosed that may allow for managing credits and tokens as part of flow control method. The local interface unit may include a transmit unit and a receive unit. The transmit unit may be configured to receive credits and tokens, determine an available number of credits based on the number received tokens, determine an available number of tokens based on the number of received tokens, and send the available credits to an arbitration unit. The available credits may then be updated, by the transmit unit in response to receiving a selected transaction from the arbitration, and the transmit unit may then transmit the selected transaction, and update the available credits and the available tokens once the transaction has been sent. The receive unit may be configured to send credits and tokens to a transmit unit, and receive a transaction sent by a transmit unit.

Abstract translation: 公开了本地接口单元的实施例，其可以允许作为流控制方法的一部分来管理信用和令牌。 本地接口单元可以包括发送单元和接收单元。 发送单元可以被配置为接收信用和令牌，基于所接收的令牌的数量来确定可用的信用数量，基于接收到的令牌的数量确定令牌的可用数量，并将可用信用发送到仲裁单元。 然后可以通过发送单元响应于从仲裁接收到所选择的交易而更新可用信用，并且发送单元然后可以发送所选择的交易，并且一旦交易被发送，就更新可用信用和可用令牌。 接收单元可以被配置为向发送单元发送信用和令牌，并且接收由发送单元发送的交易。

公开(公告)号：US20140304441A1

公开(公告)日：2014-10-09

申请号：US13859000

申请日：2013-04-09

Applicant: APPLE INC.

Inventor： Deniz Balkan ,  Gurjeet S. Saund ,  Joseph P. Bratt ,  Kevin C. Wong ,  Manu Gulati ,  Rohit K. Gupta

IPC: G06F13/38

CPC classification number: G06F13/385

Abstract: Embodiments of a bridge circuit and system are disclosed that may allow converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The second bus may include a plurality of virtual channels. The bridge circuit may be configured to receive transactions over the first bus, and convert the transactions to the second communication protocol, and to assign the converted transaction to one of the plurality of virtual channels. The bridge circuit may be further configured store the converted transaction. A plurality of limited throughput signals may be generated by the bridge circuit dependent upon a number of available credits for the plurality of virtual channels.

Abstract translation: 公开了桥接电路和系统的实施例，其可以允许将事务从一个通信协议转换到另一个通信协议。 桥接电路可以耦合到采用第一通信协议的第一总线，以及采用第二通信协议的第二总线。 第二总线可以包括多个虚拟通道。 桥接电路可以被配置为通过第一总线接收事务，并将事务转换为第二通信协议，并将转换的事务分配给多个虚拟通道中的一个。 可以进一步配置桥接电路来存储转换的事务。 取决于多个虚拟信道的可用信用数量，桥电路可以产生多个有限吞吐量信号。

公开(公告)号：US20140181571A1

公开(公告)日：2014-06-26

申请号：US13726437

申请日：2012-12-24

Applicant: APPLE INC.

Inventor： Jason M. Kassoff ,  Kevin C. Wong ,  Brian P. Lilly ,  Gurjeet S. Saund

IPC: G06F1/06

CPC classification number: G06F5/06 ,  G06F13/38 ,  G06F13/382

Abstract: Systems and methods for managing fast to slow links in a bus fabric. A pair of link interface units connect agents with a clock mismatch. Each link interface unit includes an asynchronous FIFO for storing transactions that are sent over the clock domain crossing. When the command for a new transaction is ready to be sent while data for the previous transaction is still being sent, the link interface unit prevents the last data beat of the previous transaction from being sent. Instead, after a delay of one or more clock cycles, the last data beat overlaps with the command of the new transaction.

Abstract translation: 用于管理总线结构中快速到慢速链接的系统和方法。 一对链路接口单元连接具有时钟不匹配的代理。 每个链路接口单元包括用于存储通过时钟域穿越发送的事务的异步FIFO。 当新的事务的命令准备好发送，而前一个事务的数据仍然被发送时，链接接口单元阻止发送先前事务的最后数据节拍。 相反，在一个或多个时钟周期的延迟之后，最后的数据跳转与新事务的命令重叠。

公开(公告)号：US12248369B2

公开(公告)日：2025-03-11

申请号：US18323178

申请日：2023-05-24

Applicant: Apple Inc.

Inventor： Farid Nemati ,  Steven R. Hutsell ,  Gregory S. Mathews ,  Yi Chun Chen ,  Kevin C. Wong ,  Kalpana Bansal

IPC: G06F11/10 ,  G06F11/07

Abstract: Techniques are disclosed relating to improving memory reliability. In some embodiments, memory circuitry includes memory cells configured to store data, interface circuitry, and on-die error correcting code (ECC) circuitry. The ECC circuitry may check read data from the memory cells for errors and correct detected correctable errors to generate corrected data. The memory circuitry may provide read data to a requesting circuit via the interface circuitry, including one or more sets of corrected data from the on-die ECC circuitry. The memory circuitry may provide a decoding status flag (DSF) via the interface circuitry, including to: set the DSF to a first value in response to no error being detected for a given set of provided read data, set the DSF to a second value in response to a correctable error that was detected and corrected by the on-die ECC circuitry to provide a given set of read data, and set the DSF to a third value in response to an uncorrectable error detected by the on-die ECC circuitry.

公开(公告)号：US20230251930A1

公开(公告)日：2023-08-10

申请号：US17804932

申请日：2022-06-01

Applicant: Apple Inc.

Inventor： Farid Nemati ,  Steven R. Hutsell ,  Gregory S. Mathews ,  Yi Chun Chen ,  Kevin C. Wong ,  Kalpana Bansal

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1064 ,  G06F11/106 ,  G06F11/076 ,  G06F11/0772

Abstract: Techniques are disclosed relating to improving memory reliability, e.g., in the context of memory circuits with limited reliability features. In some embodiments, memory controller circuitry is configured to communicate with memory circuitry via an interface that supports link error detection. The memory controller circuitry may, based on a corruption indicator, transmit a data and parity combination for the first data block that causes the memory circuitry to detect an uncorrectable write interface error. Subsequent reads of the location may therefore cause an uncorrectable error indication. This may advantageously allow the memory controller circuitry to propagate a corruption indicator as an uncorrectable error in the memory circuit, without requiring additional tracking of the indicator by the memory circuit or memory controller, in some embodiments.

公开(公告)号：US09639143B2

公开(公告)日：2017-05-02

申请号：US14876922

申请日：2015-10-07

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Gurjeet S. Saund ,  Munetoshi Fukami ,  Shane J. Keil ,  Chaitanya Kosaraju ,  Erdem Guleyupoglu ,  Jason M. Kassoff ,  Kevin C. Wong

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/329 ,  G06F1/3293 ,  Y02D10/24 ,  Y02D50/20

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

公开(公告)号：US11829242B2

公开(公告)日：2023-11-28

申请号：US17804932

申请日：2022-06-01

Applicant: Apple Inc.

Inventor： Farid Nemati ,  Steven R. Hutsell ,  Gregory S. Mathews ,  Yi Chun Chen ,  Kevin C. Wong ,  Kalpana Bansal

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1064 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/106

Abstract: Techniques are disclosed relating to improving memory reliability, e.g., in the context of memory circuits with limited reliability features. In some embodiments, memory controller circuitry is configured to communicate with memory circuitry via an interface that supports link error detection. The memory controller circuitry may, based on a corruption indicator, transmit a data and parity combination for the first data block that causes the memory circuitry to detect an uncorrectable write interface error. Subsequent reads of the location may therefore cause an uncorrectable error indication. This may advantageously allow the memory controller circuitry to propagate a corruption indicator as an uncorrectable error in the memory circuit, without requiring additional tracking of the indicator by the memory circuit or memory controller, in some embodiments.

公开(公告)号：US09170768B2

公开(公告)日：2015-10-27

申请号：US13726437

申请日：2012-12-24

Applicant: Apple Inc.

Inventor： Jason M. Kassoff ,  Kevin C. Wong ,  Brian P. Lilly ,  Gurjeet S. Saund

IPC: G06F5/06 ,  G06F13/38

CPC classification number: G06F5/06 ,  G06F13/38 ,  G06F13/382

Abstract: Systems and methods for managing fast to slow links in a bus fabric. A pair of link interface units connect agents with a clock mismatch. Each link interface unit includes an asynchronous FIFO for storing transactions that are sent over the clock domain crossing. When the command for a new transaction is ready to be sent while data for the previous transaction is still being sent, the link interface unit prevents the last data beat of the previous transaction from being sent. Instead, after a delay of one or more clock cycles, the last data beat overlaps with the command of the new transaction.

Abstract translation: 用于管理总线结构中快速到慢速链接的系统和方法。 一对链路接口单元连接具有时钟不匹配的代理。 每个链路接口单元包括用于存储通过时钟域穿越发送的事务的异步FIFO。 当新事务的命令准备好发送，而前一个事务的数据仍然被发送时，链接接口单元阻止发送先前事务的最后数据节拍。 相反，在一个或多个时钟周期的延迟之后，最后的数据跳转与新事务的命令重叠。

公开(公告)号：US20160026234A1

公开(公告)日：2016-01-28

申请号：US14876922

申请日：2015-10-07

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Gurjeet S. Saund ,  Munetoshi Fukami ,  Shane J. Keil ,  Chaitanya Kosaraju ,  Erdem Guleyupoglu ,  Jason M. Kassoff ,  Kevin C. Wong

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/329 ,  G06F1/3293 ,  Y02D10/24 ,  Y02D50/20

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

Abstract translation: 公开了用于接口动态硬件功率管理块和软件功率管理块的方法和装置。 在一个实施例中，集成电路（IC）可以包括多个功率可管理的功能单元。 功能单元可以通过硬件，软件或两者进行功率管理。 每个功能单元可以通过直接通信链路耦合到至少一个其它功能单元。 链路状态机可以监视功能单元之间的每个通信链路，并且可以将链路可用性的指示广播到耦合到链路的功能单元。 响应于关闭给定链路的软件请求或耦合到链路的功能单元之一的硬件启动关机，链路状态机可以广播并指示链路不可用。

公开(公告)号：US09053058B2

公开(公告)日：2015-06-09

申请号：US13721665

申请日：2012-12-20

Applicant: Apple Inc.

Inventor： Gurjeet S. Saund ,  Deniz Balkan ,  Kevin C. Wong

IPC: H04L12/54 ,  G06F13/14

CPC classification number: G06F13/14 ,  G06F13/1642 ,  G06F13/1673

Abstract: Systems and methods for upgrading QoS levels of older transactions based on the presence of higher level QoS transactions in a given queue. A counter may be maintained to track the number of transactions in a queue that are assigned a corresponding QoS level. Each separate QoS level can have a corresponding counter. When a transaction is received by the queue, the counter corresponding to the QoS level of the transaction is incremented. When a transaction leaves the queue, the transaction is upgraded to the highest QoS level with a non-zero counter. Also, when the transaction leaves the queue, the counter corresponding to the original QoS level of the transaction is decremented.

Abstract translation: 基于在给定队列中存在较高级别的QoS事务，升级旧事务的QoS级别的系统和方法。 可以维护计数器来跟踪被分配相应QoS级别的队列中的事务的数量。 每个单独的QoS级别可以有一个相应的计数器。 当队列接收到事务时，增加对应于事务的QoS级别的计数器。 当事务离开队列时，事务将使用非零计数器升级到最高的QoS级别。 此外，当事务离开队列时，对应于事务的原始QoS级别的计数器递减。