公开(公告)号：US10734983B1

公开(公告)日：2020-08-04

申请号：US16277263

申请日：2019-02-15

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Yanzhe Liu

IPC: G11C11/409 ,  H03K3/017 ,  H03K5/156

Abstract: A method and apparatus for performing duty cycle correction with read/write calibrations is disclosed. A first calibration is performed in a memory subsystem having a memory and a memory controller. The first calibration includes conveying a first clock signal from the memory controller to the memory, and determining the duty cycle of the first clock signal. If the duty cycle is not within a specified range, the duty cycle is adjusted and the process repeated. After the duty cycle of the first clock signal is within the specified range, a second calibration is performed, the second calibration including conveying a second clock signal from the memory to the memory controller. The duty cycle of the first clock signal may be further adjusted based on the second calibration.

公开(公告)号：US20200057579A1

公开(公告)日：2020-02-20

申请号：US16104307

申请日：2018-08-17

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Peter Fu ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Shane J. Keil

IPC: G06F3/06

Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller implements a per-bank priority-based arbitration scheme for different types of memory traffic (e.g., with different quality of service parameters). In some embodiments, the memory controller is configured to provide per-bank overrides to the arbitration scheme based on latency tolerance reported by one or more requesters sending a particular type of memory traffic. Various techniques disclosed herein may improve performance, improve fairness among different types of memory traffic, and/or reduce power consumption.

公开(公告)号：US10545701B1

公开(公告)日：2020-01-28

申请号：US16104307

申请日：2018-08-17

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Peter Fu ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Shane J. Keil

IPC: G06F3/06

Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller implements a per-bank priority-based arbitration scheme for different types of memory traffic (e.g., with different quality of service parameters). In some embodiments, the memory controller is configured to provide per-bank overrides to the arbitration scheme based on latency tolerance reported by one or more requesters sending a particular type of memory traffic. Various techniques disclosed herein may improve performance, improve fairness among different types of memory traffic, and/or reduce power consumption.

公开(公告)号：US12118249B2

公开(公告)日：2024-10-15

申请号：US18497883

申请日：2023-10-30

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Shane J. Keil ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Tao Zhang

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0644 ,  G06F3/0673 ,  G06F13/1605

Abstract: Systems, apparatuses, and methods for addressing bank hotspotting are described. A computing system includes a memory controller with an arbiter for determining how to arbitrate access to one or more memory device(s) for received requests. The arbiter categorizes each request in a manner that helps to ensure fair virtual channel distribution across the banks of the memory device(s). The category system includes bank hotspotting functions to give banks that have more requests more chances to go over banks with fewer requests. The category system is implemented proportionally with more category credits given to banks with higher bank depths within the virtual channel.

公开(公告)号：US10678478B2

公开(公告)日：2020-06-09

申请号：US16112624

申请日：2018-08-24

Applicant: Apple Inc.

Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Kai Lun Hsiung ,  Yanzhe Liu ,  Sukalpa Biswas

IPC: G06F3/06

Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

公开(公告)号：US20190385670A1

公开(公告)日：2019-12-19

申请号：US16012427

申请日：2018-06-19

Applicant: Apple Inc.

Inventor： Rakesh L. Notani ,  Lakshmi Narasimha Murthy Nukala ,  Kai Lun Hsiung ,  Sukalpa Biswas ,  Yanzhe Liu

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4074 ,  G06F13/16

Abstract: A method and apparatus for optimizing calibrations of a memory subsystem is disclosed. A memory controller of a memory subsystem includes a memory interface suitable for coupling to a DRAM having a plurality of banks. The memory controller includes a state machine the state machine may initiate calibration of circuitry within the memory controller. Responsive to initiating the calibration, the state machine also causes a refresh command to be transmitted to the DRAM. The calibration is then performed concurrent with the refresh of the DRAM. Subsequent to transmitting the refresh command, the state machine causes the memory interface to be placed into a low power state.

公开(公告)号：US09478263B2

公开(公告)日：2016-10-25

申请号：US14158404

申请日：2014-01-17

Applicant: Apple Inc.

Inventor： Bin Ni ,  Kai Lun Charles Hsiung ,  Yanzhe Liu ,  Sukalpa Biswas

IPC: G11C7/10 ,  G06F12/10 ,  G11C11/408 ,  G11C11/409

CPC classification number: G11C7/1072 ,  G06F12/1036 ,  G11C11/408 ,  G11C11/409

Abstract: Systems and methods for monitoring and controlling repetitive accesses to a dynamic random-access memory (DRAM) row are disclosed. A method for monitoring and controlling repetitive accesses to a DRAM can include dividing a bank of the DRAM into a number of logical blocks, mapping each row of the bank to one of the logical blocks, monitoring accesses to the logical blocks, and controlling accesses to the logical blocks based on the monitoring.

Abstract translation: 公开了用于监控和控制对动态随机存取存储器（DRAM）行的重复访问的系统和方法。 用于监测和控制对DRAM的重复访问的方法可以包括将DRAM的一组划分成多个逻辑块，将存储体的每一行映射到逻辑块之一，监视对逻辑块的访问，以及控制对 基于监控的逻辑块。

公开(公告)号：US20200301615A1

公开(公告)日：2020-09-24

申请号：US16896027

申请日：2020-06-08

Applicant: Apple Inc.

Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Kai Lun Hsiung ,  Yanzhe Liu ,  Sukalpa Biswas

IPC: G06F3/06

Abstract: An apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

公开(公告)号：US20200159463A1

公开(公告)日：2020-05-21

申请号：US16751975

申请日：2020-01-24

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Peter Fu ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Shane J. Keil

IPC: G06F3/06

Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.

公开(公告)号：US20200065028A1

公开(公告)日：2020-02-27

申请号：US16112624

申请日：2018-08-24

Applicant: Apple Inc.

Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Kai Lun Hsiung ,  Yanzhe Liu ,  Sukalpa Biswas

IPC: G06F3/06

Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.