公开(公告)号：US20200285406A1

公开(公告)日：2020-09-10

申请号：US16293398

申请日：2019-03-05

申请人： Apple Inc.

发明人： Rakesh L. Notani ,  Robert E. Jeter ,  Suhas Kumar Suvarna Ramesh ,  Naveen Kumar Korada ,  Mohammad Rizwan ,  Alma L. Juarez Dominguez ,  John H. Kelm ,  Matthew R. Johnson

IPC分类号： G06F3/06 ,  G11C11/4063 ,  G11C7/22

摘要： Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.

公开(公告)号：US09698797B1

公开(公告)日：2017-07-04

申请号：US15210852

申请日：2016-07-14

申请人： Apple Inc.

发明人： Manu Gulati ,  Suhas Kumar Suvarna Ramesh ,  Venkata Ramana Malladi ,  Thomas H. Huang ,  Rakesh L. Notani ,  Robert E. Jeter ,  Kai Lun Hsiung

IPC分类号： H03L7/00 ,  H03L7/07 ,  H03L7/099

CPC分类号： H03L7/23

摘要： Techniques are disclosed relating to feedback-controlled oscillators (e.g., phase-locked loops) arranged in two or more levels. In some embodiments, in a relatively higher-frequency mode, a first level feedback-controlled oscillator provides reference signals to one or more second level feedback-controlled oscillators that in turn generate output clock signals to clock sequential circuitry. In some embodiments, in a relatively lower-frequency mode, the first level feedback-controlled oscillator bypasses the second level feedback-controlled oscillators and provides output clock signals directly to sequential circuitry (without using any intervening feedback-controlled oscillators).

公开(公告)号：US11226752B2

公开(公告)日：2022-01-18

申请号：US16293398

申请日：2019-03-05

申请人： Apple Inc.

发明人： Rakesh L. Notani ,  Robert E. Jeter ,  Suhas Kumar Suvarna Ramesh ,  Naveen Kumar Korada ,  Mohammad Rizwan ,  Alma L. Juarez Dominguez ,  John H. Kelm ,  Matthew R. Johnson

IPC分类号： G06F3/06 ,  G11C7/22 ,  G11C11/4063 ,  G11C7/10

摘要： Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.