公开(公告)号：US11436049B2

公开(公告)日：2022-09-06

申请号：US16852107

申请日：2020-04-17

Applicant: Apple Inc.

Inventor： Nachiappan Chidambaram Nachiappan ,  Matthew R. Johnson ,  Vinodh R. Cuppu

IPC: G06F9/48 ,  G06F13/16 ,  H04L41/0896 ,  G06F9/50 ,  H04L41/046

Abstract: Systems, apparatuses, and methods for controlling bandwidth through shared transaction limits are described. An apparatus includes at least a plurality of agents, a plurality of transaction-limit (T-Limit) nodes, a T-Limit manager, and one or more endpoints. The T-Limit manager creates a plurality of credits for the plurality of agents to send transactions to a given endpoint. Then, the T-Limit manager partitions the credits into N+1 portions for N agents, wherein the extra N+1 portion is a shared pool for use by agents when they run out of their private credits. The T-Limit manager assigns a separate private portion of the N portions to the N agents for use by only the corresponding agent. When an agent runs out of private credits, the agent's T-Limit node sends a request to the T-Limit manager for credits from the shared pool.

公开(公告)号：US11809906B2

公开(公告)日：2023-11-07

申请号：US17902452

申请日：2022-09-02

Applicant: Apple Inc.

Inventor： Nachiappan Chidambaram Nachiappan ,  Matthew R. Johnson ,  Vinodh R. Cuppu

IPC: G06F9/48 ,  G06F13/16 ,  H04L41/0896 ,  G06F9/50 ,  H04L41/046

CPC classification number: G06F9/4881 ,  G06F13/161 ,  G06F13/1668 ,  H04L41/0896

Abstract: Systems, apparatuses, and methods for controlling bandwidth through shared transaction limits are described. An apparatus includes at least a plurality of agents, a plurality of transaction-limit (T-Limit) nodes, a T-Limit manager, and one or more endpoints. The T-Limit manager creates a plurality of credits for the plurality of agents to send transactions to a given endpoint. Then, the T-Limit manager partitions the credits into N+1 portions for N agents, wherein the extra N+1 portion is a shared pool for use by agents when they run out of their private credits. The T-Limit manager assigns a separate private portion of the N portions to the N agents for use by only the corresponding agent. When an agent runs out of private credits, the agent's T-Limit node sends a request to the T-Limit manager for credits from the shared pool.

公开(公告)号：US20200285406A1

公开(公告)日：2020-09-10

申请号：US16293398

申请日：2019-03-05

Applicant: Apple Inc.

Inventor： Rakesh L. Notani ,  Robert E. Jeter ,  Suhas Kumar Suvarna Ramesh ,  Naveen Kumar Korada ,  Mohammad Rizwan ,  Alma L. Juarez Dominguez ,  John H. Kelm ,  Matthew R. Johnson

IPC: G06F3/06 ,  G11C11/4063 ,  G11C7/22

Abstract: Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.

公开(公告)号：US20210326169A1

公开(公告)日：2021-10-21

申请号：US16852107

申请日：2020-04-17

Applicant: Apple Inc.

Inventor： Nachiappan Chidambaram Nachiappan ,  Matthew R. Johnson ,  Vinodh R. Cuppu

IPC: G06F9/46 ,  G06F9/48

Abstract: Systems, apparatuses, and methods for controlling bandwidth through shared transaction limits are described. An apparatus includes at least a plurality of agents, a plurality of transaction-limit (T-Limit) nodes, a T-Limit manager, and one or more endpoints. The T-Limit manager creates a plurality of credits for the plurality of agents to send transactions to a given endpoint. Then, the T-Limit manager partitions the credits into N+1 portions for N agents, wherein the extra N+1 portion is a shared pool for use by agents when they run out of their private credits. The T-Limit manager assigns a separate private portion of the N portions to the N agents for use by only the corresponding agent. When an agent runs out of private credits, the agent's T-Limit node sends a request to the T-Limit manager for credits from the shared pool.

公开(公告)号：US20220413908A1

公开(公告)日：2022-12-29

申请号：US17902452

申请日：2022-09-02

Applicant: Apple Inc.

Inventor： Nachiappan Chidambaram Nachiappan ,  Matthew R. Johnson ,  Vinodh R. Cuppu

IPC: G06F9/48 ,  G06F13/16 ,  H04L41/0896

Abstract: Systems, apparatuses, and methods for controlling bandwidth through shared transaction limits are described. An apparatus includes at least a plurality of agents, a plurality of transaction-limit (T-Limit) nodes, a T-Limit manager, and one or more endpoints. The T-Limit manager creates a plurality of credits for the plurality of agents to send transactions to a given endpoint. Then, the T-Limit manager partitions the credits into N+1 portions for N agents, wherein the extra N+1 portion is a shared pool for use by agents when they run out of their private credits. The T-Limit manager assigns a separate private portion of the N portions to the N agents for use by only the corresponding agent. When an agent runs out of private credits, the agent's T-Limit node sends a request to the T-Limit manager for credits from the shared pool.

公开(公告)号：US11226752B2

公开(公告)日：2022-01-18

申请号：US16293398

申请日：2019-03-05

Applicant: Apple Inc.

Inventor： Rakesh L. Notani ,  Robert E. Jeter ,  Suhas Kumar Suvarna Ramesh ,  Naveen Kumar Korada ,  Mohammad Rizwan ,  Alma L. Juarez Dominguez ,  John H. Kelm ,  Matthew R. Johnson

IPC: G06F3/06 ,  G11C7/22 ,  G11C11/4063 ,  G11C7/10

Abstract: Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.

公开(公告)号：US10037073B1

公开(公告)日：2018-07-31

申请号：US15273925

申请日：2016-09-23

Applicant: Apple Inc.

Inventor： Edvin Catovic ,  Rajat Goel ,  Richard F. Russo ,  Matthew R. Johnson ,  Shingo Suzuki ,  Pradeep Kanapathipillai ,  Raghava Rao V. Denduluri ,  Pankaj Lnu

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3243

Abstract: A processor includes an instruction issue circuit, and high-utilization and low-utilization execution unit circuits coupled to execute instructions received from the instruction issue unit. On average, utilization of the low-utilization execution unit circuit is lower than utilization of the high-utilization execution unit circuit. The processor also includes a retention circuit coupled to a different power domain than the low-utilization execution unit circuit, and a power management circuit. The power management circuit may be configured to detect that inactivity of the low-utilization execution unit circuit satisfies a threshold inactivity level; upon detecting that the threshold inactivity level is satisfied, cause architecturally-visible state of the low-utilization execution unit circuit to be copied to the retention circuit; and subsequent to copying of the architecturally-visible state to the retention circuit, cause the low-utilization execution unit circuit to enter a power-off state, where the retention circuit retains stored data during the power-off state.