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公开(公告)号：US10037073B1
公开(公告)日：2018-07-31
申请号：US15273925
申请日：2016-09-23
Applicant: Apple Inc.
Inventor： Edvin Catovic , Rajat Goel , Richard F. Russo , Matthew R. Johnson , Shingo Suzuki , Pradeep Kanapathipillai , Raghava Rao V. Denduluri , Pankaj Lnu
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/3206 , G06F1/3228 , G06F1/3243
Abstract: A processor includes an instruction issue circuit, and high-utilization and low-utilization execution unit circuits coupled to execute instructions received from the instruction issue unit. On average, utilization of the low-utilization execution unit circuit is lower than utilization of the high-utilization execution unit circuit. The processor also includes a retention circuit coupled to a different power domain than the low-utilization execution unit circuit, and a power management circuit. The power management circuit may be configured to detect that inactivity of the low-utilization execution unit circuit satisfies a threshold inactivity level; upon detecting that the threshold inactivity level is satisfied, cause architecturally-visible state of the low-utilization execution unit circuit to be copied to the retention circuit; and subsequent to copying of the architecturally-visible state to the retention circuit, cause the low-utilization execution unit circuit to enter a power-off state, where the retention circuit retains stored data during the power-off state.
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公开(公告)号：US20200373915A1
公开(公告)日：2020-11-26
申请号：US16989621
申请日：2020-08-10
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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Patent Agency Ranking
公开(公告)号：US11870442B2
公开(公告)日：2024-01-09
申请号：US17812089
申请日：2022-07-12
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
CPC classification number: H03K3/0372 , G06F1/08 , G06F1/28
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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公开(公告)号：US20220345117A1
公开(公告)日：2022-10-27
申请号：US17812089
申请日：2022-07-12
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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公开(公告)号：US11418173B2
公开(公告)日：2022-08-16
申请号：US16989621
申请日：2020-08-10
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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公开(公告)号：US10742201B2
公开(公告)日：2020-08-11
申请号：US16243954
申请日：2019-01-09
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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公开(公告)号：US20200106425A1
公开(公告)日：2020-04-02
申请号：US16243954
申请日：2019-01-09
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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