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公开(公告)号：US11762413B2
公开(公告)日：2023-09-19
申请号：US17476307
申请日：2021-09-15
Applicant: Apple Inc.
Inventor： Suresh Balasubramanian , Sunil Bhosekar , Bruce Andrew Doyle , Chad O. Lackey , Sharath R. Srinivasan , Erick O. Torres , Khaled M. Alashmouny
Abstract: Systems, methods, and devices are provided for calibrating and correcting a clock duty cycle. An integrated circuit may include a clock tree that provides a clock signal and a circuit that is sensitive to clock duty cycle that receives the clock signal at a lower level of the clock tree. A first duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a first target duty cycle at a higher level of the clock tree. A second duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a second target duty cycle at the lower level of the clock tree.
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公开(公告)号：US20220103166A1
公开(公告)日：2022-03-31
申请号：US17476307
申请日：2021-09-15
Applicant: Apple Inc.
Inventor： Suresh Balasubramanian , Sunil Bhosekar , Bruce Andrew Doyle , Chad O. Lackey , Sharath R. Srinivasan , Erick O. Torres , Khaled M. Alashmouny
Abstract: Systems, methods, and devices are provided for calibrating and correcting a clock duty cycle. An integrated circuit may include a clock tree that provides a clock signal and a circuit that is sensitive to clock duty cycle that receives the clock signal at a lower level of the clock tree. A first duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a first target duty cycle at a higher level of the clock tree. A second duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a second target duty cycle at the lower level of the clock tree.
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公开(公告)号：US20200373915A1
公开(公告)日：2020-11-26
申请号：US16989621
申请日：2020-08-10
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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Patent Agency Ranking
公开(公告)号：US11870442B2
公开(公告)日：2024-01-09
申请号：US17812089
申请日：2022-07-12
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
CPC classification number: H03K3/0372 , G06F1/08 , G06F1/28
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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公开(公告)号：US20220345117A1
公开(公告)日：2022-10-27
申请号：US17812089
申请日：2022-07-12
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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公开(公告)号：US11418173B2
公开(公告)日：2022-08-16
申请号：US16989621
申请日：2020-08-10
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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公开(公告)号：US10742201B2
公开(公告)日：2020-08-11
申请号：US16243954
申请日：2019-01-09
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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公开(公告)号：US20200106425A1
公开(公告)日：2020-04-02
申请号：US16243954
申请日：2019-01-09
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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