公开(公告)号：US09843330B1

公开(公告)日：2017-12-12

申请号：US15272526

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Hubert Attah ,  Jay B. Fletcher ,  Erick O. Torres ,  Fabio Gozzini

IPC: H03K21/02 ,  H03K19/21

CPC classification number: H03K21/026 ,  H02M3/157 ,  H03K19/21

Abstract: An apparatus is disclosed, including a driver circuit, a comparator circuit, and a counter circuit. The driver circuit may be configured to source a current to a load circuit. The comparator circuit may be configured to perform a comparison of a reference voltage to a voltage across the load circuit. The counter circuit may be configured to modify a digital count value based on the comparison. The driver circuit may be further configured to adjust a value of the current using the digital count value.

公开(公告)号：US11762413B2

公开(公告)日：2023-09-19

申请号：US17476307

申请日：2021-09-15

Applicant: Apple Inc.

Inventor： Suresh Balasubramanian ,  Sunil Bhosekar ,  Bruce Andrew Doyle ,  Chad O. Lackey ,  Sharath R. Srinivasan ,  Erick O. Torres ,  Khaled M. Alashmouny

IPC: G06F1/10 ,  G06F1/08

CPC classification number: G06F1/10 ,  G06F1/08

Abstract: Systems, methods, and devices are provided for calibrating and correcting a clock duty cycle. An integrated circuit may include a clock tree that provides a clock signal and a circuit that is sensitive to clock duty cycle that receives the clock signal at a lower level of the clock tree. A first duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a first target duty cycle at a higher level of the clock tree. A second duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a second target duty cycle at the lower level of the clock tree.

公开(公告)号：US20220103166A1

公开(公告)日：2022-03-31

申请号：US17476307

申请日：2021-09-15

Applicant: Apple Inc.

Inventor： Suresh Balasubramanian ,  Sunil Bhosekar ,  Bruce Andrew Doyle ,  Chad O. Lackey ,  Sharath R. Srinivasan ,  Erick O. Torres ,  Khaled M. Alashmouny

IPC: H03K5/156 ,  G11C7/22 ,  G06F1/08 ,  G06F1/10

Abstract: Systems, methods, and devices are provided for calibrating and correcting a clock duty cycle. An integrated circuit may include a clock tree that provides a clock signal and a circuit that is sensitive to clock duty cycle that receives the clock signal at a lower level of the clock tree. A first duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a first target duty cycle at a higher level of the clock tree. A second duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a second target duty cycle at the lower level of the clock tree.