公开(公告)号：US20240078029A1

公开(公告)日：2024-03-07

申请号：US17929212

申请日：2022-09-01

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Jingkui Zheng ,  Ritesh J. Shah ,  Veera Chockalingam ,  Naveen Kumar Korada

IPC: G06F3/06 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G06F3/0632 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0673 ,  G11C11/4076 ,  G11C11/4096

Abstract: Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.

公开(公告)号：US20240295976A1

公开(公告)日：2024-09-05

申请号：US18658740

申请日：2024-05-08

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Jingkui Zheng ,  Ritesh J. Shah ,  Veera Chockalingam ,  Naveen Kumar Korada

IPC: G06F3/06 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/50

CPC classification number: G06F3/0632 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0673 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/50

Abstract: Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.

公开(公告)号：US12014060B2

公开(公告)日：2024-06-18

申请号：US17929212

申请日：2022-09-01

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Jingkui Zheng ,  Ritesh J. Shah ,  Veera Chockalingam ,  Naveen Kumar Korada

IPC: G11C29/00 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/50

CPC classification number: G06F3/0632 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0673 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/50

Abstract: Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.