公开(公告)号：US12216161B2

公开(公告)日：2025-02-04

申请号：US18323946

申请日：2023-05-25

Applicant: Apple Inc.

Inventor： Bo Yang ,  Antonietta Oliva ,  Michael R. Seningen ,  Vasu P. Ganti ,  Vijay M. Bettada

IPC: G01R31/00 ,  G01R31/3185

Abstract: An apparatus includes a plurality of circuit blocks, a plurality of scan-enabled flip-flop circuits, and a plurality of scan signature circuits. The plurality of scan-enabled flip-flop circuits may be coupled in a sequential manner across the plurality of circuit blocks, and be configured to shift a scan chain test signal from a test input interface to a test output interface. The plurality of scan signature circuits may be coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and be configured to, in response to a particular test signal, concurrently load a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits. The plurality of scan-enabled flip-flop circuits may be further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface.

公开(公告)号：US20240088032A1

公开(公告)日：2024-03-14

申请号：US17932182

申请日：2022-09-14

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Chi Nung Ni ,  Chueh-An Hsieh ,  Rekha Govindaraj ,  Jun Zhai ,  Long Huang ,  Rohan U. Mandrekar ,  Saumya K. Gandhi ,  Zhuo Yan ,  Yizhang Yang ,  Saurabh P. Sinha ,  Antonietta Oliva

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5283 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/16 ,  H01L28/40 ,  H01L2224/08265 ,  H01L2224/16225

Abstract: Microelectronic modules are described. In an embodiment, a microelectronic module includes a module substrate, a chip mounted onto the module substrate, and a semiconductor-based integrated passive device between the chip and the module substrate. The semiconductor-based integrated passive device may include an upper RDL stack-up with thicker wiring layers than a lower BEOL stack-up. The semiconductor-based integrated passive device may be further solder bonded or hybrid bonded with the chip.

公开(公告)号：US20240393394A1

公开(公告)日：2024-11-28

申请号：US18323946

申请日：2023-05-25

Applicant: Apple Inc.

Inventor： Bo Yang ,  Antonietta Oliva ,  Michael R. Seningen ,  Vasu P. Ganti ,  Vijay M. Bettada

IPC: G01R31/3185

Abstract: An apparatus includes a plurality of circuit blocks, a plurality of scan-enabled flip-flop circuits, and a plurality of scan signature circuits. The plurality of scan-enabled flip-flop circuits may be coupled in a sequential manner across the plurality of circuit blocks, and be configured to shift a scan chain test signal from a test input interface to a test output interface. The plurality of scan signature circuits may be coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and be configured to, in response to a particular test signal, concurrently load a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits. The plurality of scan-enabled flip-flop circuits may be further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface.

公开(公告)号：US20230298996A1

公开(公告)日：2023-09-21

申请号：US17655699

申请日：2022-03-21

Applicant: Apple Inc.

Inventor： Mohamed H. Abu-Rahma ,  Antonietta Oliva ,  Ajay Bhatia ,  Shahzad Nazar

IPC: H01L23/528 ,  H01L27/11

CPC classification number: H01L23/528 ,  H01L27/1104 ,  H01L27/1116

Abstract: Various implementations of backside and topside routing of bitlines and wordlines in memory arrays are disclosed. Bitlines in backside and topside metal layers may be alternated between adjacent bit cells in a memory array. Alternating the location of the bitlines between bit cells in the memory array may reduce bitline capacitance in a memory array. Placing wordlines in backside metal layers may allow dual wordlines to be implemented across a span of bit cells in a memory array. The dual wordlines may be alternately connected to adjacent bit cells, thereby allowing selective toggling of bit cells based on the wordline transmitting a control signal.

公开(公告)号：US09672310B1

公开(公告)日：2017-06-06

申请号：US14795013

申请日：2015-07-09

Applicant: Apple Inc.

Inventor： Antonietta Oliva ,  John G. Dorsey ,  Keith Cox ,  Norman J. Rohrer ,  Sribalan Santhanam ,  Sung Wook Kang ,  Mohamed H. Abu-Rama ,  Ashish R. Jain

IPC: G06F17/00 ,  G06F17/50 ,  G01R31/28

CPC classification number: G01R31/2894 ,  G01R31/2856 ,  G01R31/2875 ,  G01R31/2879

Abstract: In an embodiment, the amount of supply voltage guardband to prevent incorrect operation due to aging effects may be modeled using an IC-specific age model generated early in the product life cycle of the IC. For example, high temperature operating life (HTOL) testing may be performed at multiple temperatures and/or voltages to develop the IC-specific age model. The IC-specific age model may be more accurate then the calculations used to develop guardband voltage as discussed previously, which rely on the aging of a single transistor. The IC-specific age model may be used along with monitoring of the aging effects during operation of the IC to predict an amount of increased guardband voltage that is currently desirable to apply to the IC. The predicted amount may vary from about zero when the IC is new to the full amount of guardband voltage when the IC is nearing end of life.

公开(公告)号：US20240070365A1

公开(公告)日：2024-02-29

申请号：US17823644

申请日：2022-08-31

Applicant: Apple Inc.

Inventor： Emre Alptekin ,  Antonietta Oliva

IPC: G06F30/392 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/394

Abstract: A cell layout that may be implemented in FinFET devices or other FET devices is disclosed. The cell layout utilizes an isolation gate structure to provide routing between a signal input of an active gate and a backside metal layer. The isolation gate structure includes a metal fill surrounded by gate spacers. The metal fill connects between the topside layers in the device and the backside layer in the device. The metal fill may be connected to the signal input of the active gate through routing either in a topside metal layer or a metal wire placed in a topside insulating layer. The isolation gate structure can be part of any standard cell being placed at a cell boundary or inside the cell to provide access to backside signal routing. Additionally, filler cells with isolation gate structures may provide backside routing connections for adjacent functional cells.

公开(公告)号：US20250112154A1

公开(公告)日：2025-04-03

申请号：US18643907

申请日：2024-04-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Antonietta Oliva ,  Sambasivan Narayan ,  Jun Zhai ,  Vidhya Ramachandran ,  Kamal Sikka

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/367 ,  H01L23/427 ,  H01L23/473 ,  H01L23/48 ,  H01L23/522

Abstract: Chip structures and electronic modules including a power delivery network (PDN) routing structure and signal routing structure to balance power, signaling, and thermal requirements are described. In an embodiment, the chip includes a device layer, a PDN routing structure on top of the device layer, and a signal routing structure underneath the device layer.

公开(公告)号：US10067483B1

公开(公告)日：2018-09-04

申请号：US14471164

申请日：2014-08-28

Applicant: Apple Inc.

Inventor： Ching E. Ho ,  Antonietta Oliva ,  James S. Ismail ,  John G. Dorsey ,  Keith Cox ,  Norman J. Rohrer

IPC: G06Q10/06 ,  G06F17/18 ,  G05B19/4065 ,  G05B13/02 ,  G05B23/02

Abstract: In an embodiment, a lifetime controller is configured to monitor operating conditions for a device, and to control operating conditions based on the previous conditions to improve the reliability characteristics of the device while permitting strenuous use as available. For example, the lifetime controller may permit strenuous use when the device is first powered on. Once a specified amount of strenuous use has occurred, the controller may cause the operating conditions to be reduced to reduce the wear on the device, and thus help to extend the lifetime of the device. Similarly, if a device is used in less strenuous conditions, the controller may accumulate credit which may be expended by permitting the device to operate in more strenuous conditions for a period of time.

公开(公告)号：US09607125B1

公开(公告)日：2017-03-28

申请号：US14732971

申请日：2015-06-08

Applicant: Apple Inc.

Inventor： Antonietta Oliva ,  Karthik Rajagopal ,  Manoj Gopalan ,  Mini Nanua ,  Sambasivan Narayan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/76

Abstract: Embodiments of an electromigration (EM) check scheme to reduce a pessimism on current density limits by checking wire context. This methodology, in an embodiment, includes applying existing electronic design automation (EDA) flows and tools to identify potentially-failing wires based on a worst-case EM check using conservative foundry current density limits. A more accurate, context-specific check can be performed on the potentially-failing wires to eliminate one or more of the potentially-failing wires if those wires do not experience worst-case conditions and meet current density limits based on an actual context of those wires. A designer can correct remaining wires which are not eliminated by the context-specific check.

公开(公告)号：US20130055191A1

公开(公告)日：2013-02-28

申请号：US13663755

申请日：2012-10-30

Applicant: Apple Inc.

Inventor： Antonietta Oliva ,  Gregory S. Scott ,  Edgardo F. Klass ,  Vincent R. von Kaenel

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A software tool and method for analyzing the reliability or failure rate of an integrated circuit (IC) are disclosed. The IC may include a plurality of circuit designs, and the software tool and method may aid a designer of the IC in determining a reliability rating of the IC based on reliability ratings of transistors or other circuit devices used in the circuit designs. In particular, the IC may include one or more circuit designs that have multiple instances within the IC (i.e., the same circuit design is instantiated multiple times), and the software tool and method may take into account the multiple instances when determining the reliability rating of the IC.

Abstract translation: 公开了一种用于分析集成电路（IC）的可靠性或故障率的软件工具和方法。 IC可以包括多个电路设计，并且该软件工具和方法可以帮助IC的设计者基于在电路设计中使用的晶体管或其它电路器件的可靠性等级来确定IC的可靠性等级。 特别地，IC可以包括在IC内具有多个实例的一个或多个电路设计（即，相同的电路设计被实例化多次），并且当确定可靠性等级时，软件工具和方法可以考虑多个实例 的IC。