公开(公告)号：US20210356523A1

公开(公告)日：2021-11-18

申请号：US16874075

申请日：2020-05-14

Applicant: Apple Inc.

Inventor： Edgardo F. Klass

IPC: G01R31/3183 ,  G01R31/28 ,  G06F30/367

Abstract: In some embodiments, a method may include an area-aware optimization for the test patterns. The method may include dividing the chip area into a grid. The grid may be based on the smallest particle size. The method may include preparing test patterns and identifying a subset of test patterns that touch all of the grid locations. The subset may include a minimum number of test patterns from the prepared test patterns which when implemented exercise the all of the grid locations. The method allows to more quickly determine chips that fail due to extrinsic defects. Once a test fails during the testing process for a chip, testing on the chip is stopped and testing begins on the next chip. Rapidly identifying chips that fail due to extrinsic failures can decrease the overall test time and identify those that will fail quickly as the chip process matures and is dominated by extrinsic failures.

公开(公告)号：US20180013432A1

公开(公告)日：2018-01-11

申请号：US15201739

申请日：2016-07-05

Applicant: Apple Inc.

Inventor： Edgardo F. Klass

IPC: H03K19/00 ,  G06F1/10 ,  H03K19/0185 ,  H03K19/177

CPC classification number: H03K19/0016 ,  G06F1/10 ,  G06F1/3296 ,  H03K3/012 ,  H03K19/018521 ,  H03K19/17784

Abstract: In an embodiment, an integrated circuit includes a clock tree circuit and logic circuitry that is clocked by the clocks received from the clock tree circuit. The logic circuit is powered by a first power supply voltage. The integrated circuit includes a voltage regulator that receives the first power supply voltage and generates a second power supply voltage having a magnitude that is lower than the magnitude of the first power supply voltage by a predetermined amount. The second power supply voltage may track the first power supply voltage over dynamic changes during use, either intentional changes to operating state or noise-induced changes. The second power supply voltage may be used to power at least a portion of the clock tree.

公开(公告)号：US09503086B1

公开(公告)日：2016-11-22

申请号：US14855507

申请日：2015-09-16

Applicant: Apple Inc.

Inventor： Edgardo F. Klass

IPC: H03K3/00 ,  H03K19/00 ,  H03K3/037 ,  H03K17/30

CPC classification number: H03K19/0016 ,  H03K19/17736

Abstract: In an embodiment, an integrated circuit may include edge triggered flops that launch data to start a clock cycle and that capture data at the end of the clock cycle. Combinatorial logic circuitry may be coupled between the launching and capturing flops, and may be configured to operate on the launched data to generate result data for the capturing flops. One or more latches may be provided in the combinatorial logic circuitry, which may close and capture intermediate values responsive to an opposite edge of the clock than the edge that triggers the edge-triggered flops. In an embodiment, the clock to the latches may be gated with an enable. When the integrated circuit is not operating in the subthreshold voltage region, the enable may be in the disabled state. When operating in the subthreshold voltage region, the enable may be in the enabled state.

Abstract translation: 在一个实施例中，集成电路可以包括边缘触发的触发器，其启动数据以开始时钟周期并且在时钟周期结束时捕获数据。 组合逻辑电路可以耦合在发射和捕获触发器之间，并且可以被配置为对所发射的数据进行操作以生成用于捕获器的结果数据。 可以在组合逻辑电路中提供一个或多个锁存器，其可以响应于触发边沿触发的触发器的边沿的时钟的相对边缘来闭合和捕获中间值。 在一个实施例中，锁存器的时钟可以通过使能来选通。 当集成电路不工作在亚阈值电压区域时，使能可能处于禁止状态。 当在亚阈值电压区域中操作时，使能可以处于使能状态。

公开(公告)号：US20130067292A1

公开(公告)日：2013-03-14

申请号：US13672285

申请日：2012-11-08

Applicant: Apple Inc.

Inventor： Bo Tang ,  Edgardo F. Klass

IPC: G01R31/3177

CPC classification number: G01R31/318552 ,  G01R31/318594

Abstract: A number of scan flops clocked by a master clock may be used to constructing a scan chain to perform scan tests. During a scan test, data appearing at the regular data input of each scan flop may be written into a master latch of the scan flop during a time period when the scan control signal is in a state corresponding to a capture cycle. A slave latch in each scan flop may latch a value appearing at the regular data input of the scan flop according to a narrow pulse triggered by the rising edge of the master clock when the scan control signal is in the state corresponding to the capture cycle. The slave latch may latch the data provided by the master latch according to a wide pulse triggered by the rising edge of the master clock when the scan control signal is in a state corresponding to a shift cycle. This may permit toggling the scan control signal during either a high phase or a low phase of the master clock, and may also enable testing the pulse functionality of each scan flop.

Abstract translation: 可以使用由主时钟计时的多个扫描器来构建扫描链来执行扫描测试。 在扫描测试期间，在扫描控制信号处于与捕获周期对应的状态的时间段期间，出现在每个扫描触发器的常规数据输入端的数据可以写入扫描触发器的主锁存器。 当扫描控制信号处于与捕获周期对应的状态时，每个扫描触发器中的从锁存器可以根据由主时钟的上升沿触发的窄脉冲来锁存出现在扫描触发器的常规数据输入端的值。 当扫描控制信号处于与移位周期对应的状态时，从锁存器可以根据由主时钟的上升沿触发的宽脉冲来锁存由主锁存器提供的数据。 这可以允许在主时钟的高相位或低相位期间切换扫描控制信号，并且还可以使得能够测试每个扫描触发器的脉冲功能。

公开(公告)号：US20130055191A1

公开(公告)日：2013-02-28

申请号：US13663755

申请日：2012-10-30

Applicant: Apple Inc.

Inventor： Antonietta Oliva ,  Gregory S. Scott ,  Edgardo F. Klass ,  Vincent R. von Kaenel

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A software tool and method for analyzing the reliability or failure rate of an integrated circuit (IC) are disclosed. The IC may include a plurality of circuit designs, and the software tool and method may aid a designer of the IC in determining a reliability rating of the IC based on reliability ratings of transistors or other circuit devices used in the circuit designs. In particular, the IC may include one or more circuit designs that have multiple instances within the IC (i.e., the same circuit design is instantiated multiple times), and the software tool and method may take into account the multiple instances when determining the reliability rating of the IC.

Abstract translation: 公开了一种用于分析集成电路（IC）的可靠性或故障率的软件工具和方法。 IC可以包括多个电路设计，并且该软件工具和方法可以帮助IC的设计者基于在电路设计中使用的晶体管或其它电路器件的可靠性等级来确定IC的可靠性等级。 特别地，IC可以包括在IC内具有多个实例的一个或多个电路设计（即，相同的电路设计被实例化多次），并且当确定可靠性等级时，软件工具和方法可以考虑多个实例 的IC。

公开(公告)号：US11500019B2

公开(公告)日：2022-11-15

申请号：US16874075

申请日：2020-05-14

Applicant: Apple Inc.

Inventor： Edgardo F. Klass

IPC: G01R31/3183 ,  G06F30/367 ,  G01R31/28

Abstract: In some embodiments, a method may include an area-aware optimization for the test patterns. The method may include dividing the chip area into a grid. The grid may be based on the smallest particle size. The method may include preparing test patterns and identifying a subset of test patterns that touch all of the grid locations. The subset may include a minimum number of test patterns from the prepared test patterns which when implemented exercise the all of the grid locations. The method allows to more quickly determine chips that fail due to extrinsic defects. Once a test fails during the testing process for a chip, testing on the chip is stopped and testing begins on the next chip. Rapidly identifying chips that fail due to extrinsic failures can decrease the overall test time and identify those that will fail quickly as the chip process matures and is dominated by extrinsic failures.

公开(公告)号：US11204384B1

公开(公告)日：2021-12-21

申请号：US16138379

申请日：2018-09-21

Applicant: Apple Inc.

Inventor： Edgardo F. Klass

IPC: G01R31/317 ,  G06F1/3287 ,  G01R31/3187 ,  G01R31/50

Abstract: In some embodiments, a system and/or method may test logic blocks for an integrated circuit. To alleviate problems associated with current methods of integrated circuit testing, a system may include a power switch control signal on a different voltage rail. In some embodiments, a Test VDD may be used to isolate the power switches from the rest of the logic cells in an integrated circuit. During testing, each logic block may be powered individually using the Test VDD to control the power switches to the logic blocks. When a logic block short is identified, the nonviable logic block may be isolated to such that the nonviable logic block is not used during the future and only viable logic blocks are used in the integrated circuit. This allows for use of logic within an integrated circuit that might otherwise have been discarded or destroyed because of one or more shorts.

公开(公告)号：US09973191B2

公开(公告)日：2018-05-15

申请号：US15201739

申请日：2016-07-05

Applicant: Apple Inc.

Inventor： Edgardo F. Klass

IPC: H03K19/00 ,  G06F1/10 ,  H03K19/0185 ,  H03K19/177

CPC classification number: H03K19/0016 ,  G06F1/10 ,  G06F1/3296 ,  H03K3/012 ,  H03K19/018521 ,  H03K19/17784

Abstract: In an embodiment, an integrated circuit includes a clock tree circuit and logic circuitry that is clocked by the clocks received from the clock tree circuit. The logic circuit is powered by a first power supply voltage. The integrated circuit includes a voltage regulator that receives the first power supply voltage and generates a second power supply voltage having a magnitude that is lower than the magnitude of the first power supply voltage by a predetermined amount. The second power supply voltage may track the first power supply voltage over dynamic changes during use, either intentional changes to operating state or noise-induced changes. The second power supply voltage may be used to power at least a portion of the clock tree.

公开(公告)号：US08635503B2

公开(公告)日：2014-01-21

申请号：US13672285

申请日：2012-11-08

Applicant: Apple Inc.

Inventor： Bo Tang ,  Edgardo F. Klass

IPC: G01R31/28

CPC classification number: G01R31/318552 ,  G01R31/318594

Abstract: A number of scan flops clocked by a master clock may be used to constructing a scan chain to perform scan tests. During a scan test, data appearing at the regular data input of each scan flop may be written into a master latch of the scan flop during a time period when the scan control signal is in a state corresponding to a capture cycle. A slave latch in each scan flop may latch a value appearing at the regular data input of the scan flop according to a narrow pulse triggered by the rising edge of the master clock when the scan control signal is in the state corresponding to the capture cycle. The slave latch may latch the data provided by the master latch according to a wide pulse triggered by the rising edge of the master clock when the scan control signal is in a state corresponding to a shift cycle. This may permit toggling the scan control signal during either a high phase or a low phase of the master clock, and may also enable testing the pulse functionality of each scan flop.

Abstract translation: 可以使用由主时钟计时的多个扫描器来构建扫描链来执行扫描测试。 在扫描测试期间，在扫描控制信号处于与捕获周期对应的状态的时间段期间，出现在每个扫描触发器的常规数据输入端的数据可以写入扫描触发器的主锁存器。 当扫描控制信号处于与捕获周期对应的状态时，每个扫描触发器中的从锁存器可以根据由主时钟的上升沿触发的窄脉冲来锁存出现在扫描触发器的常规数据输入端的值。 当扫描控制信号处于与移位周期对应的状态时，从锁存器可以根据由主时钟的上升沿触发的宽脉冲来锁存由主锁存器提供的数据。 这可以允许在主时钟的高相位或低相位期间切换扫描控制信号，并且还可以使得能够测试每个扫描触发器的脉冲功能。