公开(公告)号：US20240393394A1

公开(公告)日：2024-11-28

申请号：US18323946

申请日：2023-05-25

Applicant: Apple Inc.

Inventor： Bo Yang ,  Antonietta Oliva ,  Michael R. Seningen ,  Vasu P. Ganti ,  Vijay M. Bettada

IPC: G01R31/3185

Abstract: An apparatus includes a plurality of circuit blocks, a plurality of scan-enabled flip-flop circuits, and a plurality of scan signature circuits. The plurality of scan-enabled flip-flop circuits may be coupled in a sequential manner across the plurality of circuit blocks, and be configured to shift a scan chain test signal from a test input interface to a test output interface. The plurality of scan signature circuits may be coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and be configured to, in response to a particular test signal, concurrently load a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits. The plurality of scan-enabled flip-flop circuits may be further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface.

公开(公告)号：US12216161B2

公开(公告)日：2025-02-04

申请号：US18323946

申请日：2023-05-25

Applicant: Apple Inc.

Inventor： Bo Yang ,  Antonietta Oliva ,  Michael R. Seningen ,  Vasu P. Ganti ,  Vijay M. Bettada

IPC: G01R31/00 ,  G01R31/3185

Abstract: An apparatus includes a plurality of circuit blocks, a plurality of scan-enabled flip-flop circuits, and a plurality of scan signature circuits. The plurality of scan-enabled flip-flop circuits may be coupled in a sequential manner across the plurality of circuit blocks, and be configured to shift a scan chain test signal from a test input interface to a test output interface. The plurality of scan signature circuits may be coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and be configured to, in response to a particular test signal, concurrently load a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits. The plurality of scan-enabled flip-flop circuits may be further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface.

公开(公告)号：US20240077531A1

公开(公告)日：2024-03-07

申请号：US18450714

申请日：2023-08-16

Applicant: Apple Inc.

Inventor： David A. Karol ,  Date J.W. Noorlag ,  Scott D. Hector ,  Vasu P. Ganti

IPC: G01R31/28

CPC classification number: G01R31/2884

Abstract: Systems and methods are provided for detecting defects caused by cracks in an integrated circuit, which may arise during or after a silicon wafer is singulated into separate integrated circuits. An integrated circuit may include crack detection circuitry including a metal circuit. The metal circuit may fracture or break due to crack propagation through a portion of the integrated circuit. In the event of a crack, testing may detect the fracture of the metal circuit. The crack detection circuitry may also detect accurate operation of circuitry of the integrated circuit.

公开(公告)号：US20250093416A1

公开(公告)日：2025-03-20

申请号：US18391145

申请日：2023-12-20

Applicant: Apple Inc.

Inventor： Bo Yang ,  Heon C. Kim ,  Vasu P. Ganti

IPC: G01R31/3185 ,  G01R31/317

Abstract: An apparatus includes a first set of scan-enabled flip-flop circuits may be configured to shift a scan-chain pattern from a first test input node to a first test output node using a first clock signal. A particular lockup latch may be coupled to the first test output node and to a second test input node. This particular lockup latch may be configured to, when enabled, delay propagation of the scan-chain pattern from the first test output node to the second test input node. A second set of scan-enabled flip-flop circuits may be configured to shift the scan-chain pattern from the second test input node to a second test output node using a second clock signal, different from the first clock signal. A control circuit may be configured to determine whether to enable the particular lockup latch using a particular scan test signal.