公开(公告)号：US20110026305A1

公开(公告)日：2011-02-03

申请号：US12903011

申请日：2010-10-12

申请人： Daniel S. Reed ,  Yong Lu ,  Andrew John Carter ,  Hai Li

发明人： Daniel S. Reed ,  Yong Lu ,  Andrew John Carter ,  Hai Li

IPC分类号： G11C11/00 ,  H01L21/82

CPC分类号： G11C13/0097 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/76

摘要： A non-volatile memory cell and associated method of use are disclosed. In accordance with various embodiments, the memory cell includes a switching device and a resistive sense element (RSE) connected in series between first and second control lines. The first control line is supplied with a variable voltage and the second control line is maintained at a fixed reference voltage. A first resistive state of the RSE is programmed by lowering the variable voltage of the first control line below the fixed reference voltage of the second control line to flow a body-drain current through the switching device. A different, second resistive state of the RSE is programmed by raising the variable voltage of the first control line above the fixed reference voltage to flow a drain-source current through the switching device.

摘要翻译： 公开了一种非易失性存储单元及其相关使用方法。 根据各种实施例，存储单元包括串联连接在第一和第二控制线之间的开关装置和电阻感测元件（RSE）。 第一控制线被提供可变电压，第二控制线保持在固定的参考电压。 RSE的第一电阻状态通过将第一控制线的可变电压降低到第二控制线的固定参考电压以下来编程，以使体电流流过开关器件。 RSE的不同的第二电阻状态通过将第一控制线的可变电压升高到固定参考电压以上而使漏源电流流过开关器件来编程。

公开(公告)号：US20100118590A1

公开(公告)日：2010-05-13

申请号：US12502001

申请日：2009-07-13

申请人： Andrew John Carter ,  Yong Lu

发明人： Andrew John Carter ,  Yong Lu

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C5/06

CPC分类号： G11C5/063 ,  G11C11/1659 ,  G11C11/1675

摘要： A bidirectional memory array architecture for non-volatile memory is disclosed. In accordance with some embodiments, a plurality of memory cells are arranged into an M number of rows and an N number of columns with each memory cell having a resistive sense element (RSE) and a switching device. A total number of M+N+1 control lines extend adjacent to and are connected with the memory cells to facilitate bi-directional programming of resistive states to each memory cell.

摘要翻译： 公开了一种用于非易失性存储器的双向存储器阵列架构。 根据一些实施例，多个存储器单元被布置成M个行和N个列，每个存储单元具有电阻读出元件（RSE）和开关器件。 M + N + 1个控制线的总数量与存储器单元相邻延伸并与存储单元连接，以促进对每个存储器单元的电阻状态的双向编程。

公开(公告)号：US08203894B2

公开(公告)日：2012-06-19

申请号：US13081170

申请日：2011-04-06

申请人： Chulmin Jung ,  Insik Jin ,  YoungPil Kim ,  Yong Lu ,  Harry Hongyue Liu ,  Andrew John Carter

发明人： Chulmin Jung ,  Insik Jin ,  YoungPil Kim ,  Yong Lu ,  Harry Hongyue Liu ,  Andrew John Carter

IPC分类号： G11C7/22

CPC分类号： G11C11/1673

摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.

摘要翻译： 一种用于从非易失性存储单元读取数据的方法和装置。 在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列，每个行和列都由线驱动器控制。 提供读取电路，其能够通过将非积分的第一参考值与非积分的第二参考值进行微分来读取预定存储器单元的逻辑状态。 此外，在配置与预定存储单元相对应的列之后立即测量每个参考值以产生第一和第二电流量。

公开(公告)号：US08045412B2

公开(公告)日：2011-10-25

申请号：US12487165

申请日：2009-06-18

申请人： Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Andrew John Carter ,  Daniel Reed

发明人： Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Andrew John Carter ,  Daniel Reed

IPC分类号： G11C7/00

CPC分类号： G11C13/0064 ,  G11C11/1675 ,  G11C11/56 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0088 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2213/79

摘要： Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.

摘要翻译： 用于将数据传送到存储器的装置和相关方法，例如电阻读出存储器（RSM）。 根据一些实施例，包括逻辑状态序列的输入数据通过在第一写入步骤期间同时向第一多个单位单元中的每个单元写入第一逻辑状态而将第一逻辑状态写入存储器块，并且同时写入 在第二写入步骤期间从序列到第二非重叠多个单位单元中的每一个的第二逻辑状态。

公开(公告)号：US20100118589A1

公开(公告)日：2010-05-13

申请号：US12424065

申请日：2009-04-15

申请人： Andrew John Carter ,  Maroun Georges Khoury ,  Yong Lu ,  Roger Glenn Rolbiecki

发明人： Andrew John Carter ,  Maroun Georges Khoury ,  Yong Lu ,  Roger Glenn Rolbiecki

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C11/14

CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1675

摘要： A non-volatile memory cell array and associated method of use are disclosed. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs.

摘要翻译： 公开了一种非易失性存储单元阵列和相关联的使用方法。 根据各种实施例，阵列包括耦合到共享交换设备的多个可编程电阻感测元件（RSE）。 开关器件具有公共源极区域和多个漏极区域，每个漏极区域与所述多个RSE连接到相关联的RSE。

公开(公告)号：US08213259B2

公开(公告)日：2012-07-03

申请号：US12903011

申请日：2010-10-12

申请人： Daniel S. Reed ,  Yong Lu ,  Andrew John Carter ,  Hai Li

发明人： Daniel S. Reed ,  Yong Lu ,  Andrew John Carter ,  Hai Li

IPC分类号： G11C7/12 ,  G11C8/08 ,  G11C11/21 ,  G11C11/02 ,  G11C7/22

CPC分类号： G11C13/0097 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/76

摘要： A non-volatile memory cell and associated method of use. In accordance with some embodiments, the memory cell includes a transistor comprising source and drain regions spanned by a gate region, and a resistive sense element (RSE) connected to the drain region of the transistor. The RSE is programmed to a first resistance by flowing a first write current through the RSE and then through the drain and source regions of the transistor. The RSE is programmed to a second resistance by flowing a second write current through the drain region and then through the RSE, the second write current bypassing the source region.

摘要翻译： 非易失性存储单元及相关联的使用方法。 根据一些实施例，存储器单元包括晶体管，其包括由栅极区域跨越的源极和漏极区域，以及连接到晶体管的漏极区域的电阻感测元件（RSE）。 通过使第一写入电流流过RSE然后通过晶体管的漏极和源极区域将RSE编程为第一电阻。 通过使第二写入电流流经漏极区域，然后通过RSE，将第二电阻编程为第二电阻，第二写入电流绕过源极区域。

公开(公告)号：US07885097B2

公开(公告)日：2011-02-08

申请号：US12501077

申请日：2009-07-10

申请人： Daniel S. Reed ,  Yong Lu ,  Andrew John Carter ,  Hai Li

发明人： Daniel S. Reed ,  Yong Lu ,  Andrew John Carter ,  Hai Li

IPC分类号： G11C7/12 ,  G11C8/12 ,  G11C11/16 ,  G11C11/02 ,  G11C11/14

CPC分类号： G11C13/0097 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/76

摘要： In accordance with various embodiments, a column of non-volatile memory cells is connected between opposing first and second control lines. A fixed reference voltage is applied to the second control line. The memory cells are simultaneously programmed to a first resistive state by applying a first voltage to the first control line that is greater than the fixed reference voltage. Less than all of the memory cells are subsequently simultaneously programmed to a different, second resistive state by applying a second voltage to the first control line that is less than the fixed reference voltage, so that at the conclusion of the respective programming steps a first portion of the memory cells along said column are at the first resistive state and a second portion of the memory cells along said column are at the second resistive state.

摘要翻译： 根据各种实施例，一列非易失性存储单元连接在相对的第一和第二控制线之间。 将固定的参考电压施加到第二控制线。 通过向第一控制线施加大于固定参考电压的第一电压，将存储单元同时编程为第一电阻状态。 随后通过向小于固定参考电压的第一控制线施加第二电压而将小于所有存储单元的数据同时编程为不同的第二电阻状态，使得在相应编程步骤结束时，第一部分 沿着所述列的存储器单元处于第一电阻状态，并且沿着所述列的存储单元的第二部分处于第二电阻状态。

公开(公告)号：US20100118602A1

公开(公告)日：2010-05-13

申请号：US12270056

申请日：2008-11-13

申请人： Andrew John Carter ,  Yiran Chen ,  Yong Lu ,  Harry Hongyue Liu

发明人： Andrew John Carter ,  Yiran Chen ,  Yong Lu ,  Harry Hongyue Liu

IPC分类号： G11C11/14

CPC分类号： G11C5/063 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C2213/72 ,  G11C2213/74

摘要： A memory array includes a plurality of first and second source, lines overlapping a plurality of bit lines, and a plurality of magnetic storage elements, each coupled to a corresponding first and second source line and to a corresponding bit line. Current may be driven, in first and second directions, through each magnetic element, for example, to program the elements. Diodes may be incorporated to avert sneak paths in the memory array. A first diode may be coupled between each magnetic element and the corresponding first source line, the first diode being biased to allow read and write current flow through the magnetic element, from the corresponding first source line; and a second diode may be coupled between each magnetic element and the corresponding second source line, the second diode being reverse-biased to block read and write current flow through the magnetic element, from the corresponding second source line.

摘要翻译： 存储器阵列包括多个第一和第二源，与多个位线重叠的线，以及多个磁存储元件，每个磁存储元件分别耦合到对应的第一和第二源极线以及相应的位线。 电流可以在第一和第二方向上通过每个磁性元件被驱动，例如编程元件。 可以并入二极管以避免存储器阵列中的潜行路径。 第一二极管可以耦合在每个磁性元件和对应的第一源极线之间，第一二极管被偏置以允许读取和写入电流从相应的第一源极线流过磁性元件; 并且第二二极管可以耦合在每个磁性元件和对应的第二源极线之间，所述第二二极管被反向偏置以阻挡从对应的第二源极线读取和写入通过磁性元件的电流。

公开(公告)号：US20100091548A1

公开(公告)日：2010-04-15

申请号：US12501077

申请日：2009-07-10

申请人： Daniel S. Reed ,  Yong Lu ,  Andrew John Carter ,  Hai Li

发明人： Daniel S. Reed ,  Yong Lu ,  Andrew John Carter ,  Hai Li

IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C7/00

CPC分类号： G11C13/0097 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/76

摘要： A non-volatile memory cell and associated method of use are disclosed. In accordance with various embodiments, the memory cell includes a switching device and a resistive sense element (RSE) connected in series between first and second control lines. The first control line is supplied with a variable voltage and the second control line is maintained at a fixed reference voltage. A first resistive state of the RSE is programmed by lowering the variable voltage of the first control line below the fixed reference voltage of the second control line to flow a body-drain current through the switching device. A different, second resistive state of the RSE is programmed by raising the variable voltage of the first control line above the fixed reference voltage to flow a drain-source current through the switching device.

摘要翻译： 公开了一种非易失性存储单元及其相关使用方法。 根据各种实施例，存储单元包括串联连接在第一和第二控制线之间的开关装置和电阻感测元件（RSE）。 第一控制线被提供可变电压，第二控制线保持在固定的参考电压。 RSE的第一电阻状态通过将第一控制线的可变电压降低到第二控制线的固定参考电压以下来编程，以使体电流流过开关器件。 RSE的不同的第二电阻状态通过将第一控制线的可变电压升高到固定参考电压以上而使漏源电流流过开关器件来编程。

公开(公告)号：US20120147659A1

公开(公告)日：2012-06-14

申请号：US13400519

申请日：2012-02-20

申请人： Andrew John Carter ,  Yong Lu

发明人： Andrew John Carter ,  Yong Lu

IPC分类号： G11C11/00

CPC分类号： G11C5/063 ,  G11C11/1659 ,  G11C11/1675

摘要： Method and apparatus for transferring data in a memory. A semiconductor memory includes a plurality of memory cells each having a resistive sense element (RSE) in series with a switching device. A conductive word line extends in a first direction adjacent the memory cells and is connected to a gate structure of each of the switching devices. A plurality of conductive bit lines extend in a second direction adjacent the memory cells, each bit line providing a connection node that interconnects a respective pair of the memory cells. A control circuit senses a programmed state of a selected memory cell by setting each of the bit lines on a first side of the selected memory cell to a first voltage level, setting each of the remaining bit lines on an opposing second side of the selected memory cell to a second voltage level, and setting the word line to a third voltage level.

摘要翻译： 用于在存储器中传送数据的方法和装置。 半导体存储器包括多个存储单元，每个存储单元具有与开关器件串联的电阻感测元件（RSE）。 导电字线在与存储器单元相邻的第一方向上延伸并且连接到每个开关器件的栅极结构。 多个导电位线在与存储单元相邻的第二方向上延伸，每个位线提供连接相应的一对存储单元的连接节点。 控制电路通过将所选择的存储器单元的第一侧上的每个位线设置为第一电压电平来感测所选择的存储器单元的编程状态，将所选择的存储器的相对的第二侧上的每个剩余位线设置 单元到第二电压电平，并将字线设置为第三电压电平。