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公开(公告)号：US20240428877A1
公开(公告)日：2024-12-26
申请号：US18340906
申请日：2023-06-26
Applicant: APPLE INC.
Inventor： Assaf Shappir , Ruby Mizrahi , Nir Tishbi , Itamar Atiya
Abstract: A storage apparatus includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells organized in multiple memory blocks. The storage circuitry is configured to produce a given readout by reading data from a group of the memory cells in a given memory block, using a given read voltage, to calculate a given zeros-ones imbalance level of the given readout, based on the given zeros-ones imbalance level, to check whether the given readout level is zeros-ones balanced or unbalanced in accordance with a balance criterion, and upon detecting that the given readout is zeros-ones unbalanced, mark the given memory block as suspected of being unusable.
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公开(公告)号：US20240087666A1
公开(公告)日：2024-03-14
申请号：US17942143
申请日：2022-09-11
Applicant: Apple Inc.
Inventor： Assaf Shappir
CPC classification number: G11C29/42 , G06F11/1048
Abstract: A controller includes an interface and circuitry. The interface communicates with memory cells arranged in multiple address locations. Storage nodes holding storage values included in the memory cells are accessible using select transistors powered by an adjustable supply voltage. The circuitry reads data units protected by an Error Correction Code (ECC) from the memory cells and decode the ECC of the data units. Upon detecting, using the ECC, that a given data unit read from a given address location contains one or more errors, the circuitry logs an error event specifying at least a time of occurrence associated with the error event and the given address location. The circuitry identifies that the select transistors experience physical degradation due to aging, based on the times of occurrence and address locations logged in the error events, and adjusts the supply voltage provided to the select transistors to compensate for the physical degradation.
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公开(公告)号：US20210264980A1
公开(公告)日：2021-08-26
申请号：US16799874
申请日：2020-02-25
Applicant: Apple Inc.
Inventor： Itay Sagron , Assaf Shappir
Abstract: A controller includes an interface and storage circuitry. The interface is configured to communicate with a memory device that includes multiple memory cells organized in memory blocks. The memory device supporting programming of the memory cells with enabled or disabled program-verification. The storage circuitry is configured to disable the program-verification, and program data to a group of the memory cells in a Single Level Cell (SLC) mode using a single programming pulse, to read the data from the group of the memory cells. In response to detecting a failure in reading the data, the storage circuitry is configured to distinguish between whether the memory cells in the group belong to a defective memory block or were under-programmed, and when identifying that the memory cells in the group were under-programmed, to perform a corrective action to prevent under-programming in subsequent program operations to the memory cells in the group.
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公开(公告)号：US10915394B1
公开(公告)日：2021-02-09
申请号：US16578353
申请日：2019-09-22
Applicant: Apple Inc.
Inventor： Assaf Shappir , Stas Mouler
IPC: G11C29/00 , G06F11/10 , G06F11/07 , G06F11/14 , H01L21/822 , G11C11/408 , G11C11/409 , G11C29/44
Abstract: A memory system includes a Nonvolatile Memory (NVM) and storage circuitry. The NVM includes memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The storage circuitry assigns in a recovery scheme, data pages to predefined parity groups, including assigning to a parity group multiple data pages of two or more different bit-significance values in a common group of the memory cells in a WL. The storage circuitry calculates redundancy data over the data pages of a given parity group in accordance with the recovery scheme and stores the redundancy data in a dedicated group of the memory cells. The storage circuitry reads a data page belonging to the given parity group, and upon detecting a read failure, recovers the data page based on other data pages in the given parity group and on the redundancy data calculated for the given parity group.
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公开(公告)号：US10332608B2
公开(公告)日：2019-06-25
申请号：US15992229
申请日：2018-05-30
Applicant: Apple Inc.
Inventor： Yael Shur , Assaf Shappir , Barak Baum , Roman Guy , Michael Tsohar
Abstract: A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.
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Patent Agency Ranking
公开(公告)号：US10296062B2
公开(公告)日：2019-05-21
申请号：US15898586
申请日：2018-02-18
Applicant: Apple Inc.
Inventor： Barak Rotbard , Assaf Shappir
Abstract: A memory controller includes an interface and a processor. The interface is configured to communicate with one or more memory devices that require an operation voltage. The memory devices are capable of obtaining the operation voltage either from a power supply external to the memory device or from respective charge pumps internal to the memory devices. The processor is configured to predict storage activity in the memory devices, and to cause the memory devices to select a source for the operation voltage between the power supply and the respective charge pumps in accordance with the predicted storage activity.
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公开(公告)号：US09928126B1
公开(公告)日：2018-03-27
申请号：US15716684
申请日：2017-09-27
Applicant: Apple Inc.
Inventor： Assaf Shappir , Moshe Neerman , Ofer Shapira
CPC classification number: G06F11/002 , G06F11/3058 , G11C7/04 , G11C11/5642
Abstract: A memory system includes an interface and storage circuitry. The interface is configured to communicate with memory cells that store data. The storage circuitry is configured to program a data unit to a first group of the memory cells, to read the data unit from the first group using at least a read threshold to produce a first readout, and in response to detecting that reading the data unit has failed because the read threshold has fallen outside a supported range of read thresholds, due to a temperature difference between a time of programming the first group and a time of reading the first group, to program a second group of the memory cells. The circuitry is further configured to re-read the data unit from the first group using the at least read threshold to produce a second readout, and to recover the data unit from the second readout.
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公开(公告)号：US20180074892A1
公开(公告)日：2018-03-15
申请号：US15265869
申请日：2016-09-15
Applicant: Apple Inc.
Inventor： Assaf Shappir , Eyal Gurgi
CPC classification number: G11C29/52 , G06F11/1048 , G11C11/22 , G11C2029/0411 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/451
Abstract: A memory controller includes an interface and circuitry. The interface is configured to communicate with a memory device, which includes multiple memory cells, and which applies refreshing to the memory cells by repeatedly inverting data stored in the memory cells. The circuitry is configured to store input data in a group of the memory cells, to read the stored input data from the group of the memory cells to produce read data, the read data has an actual polarity that is either un-inverted or inverted due to the refreshing of the memory cells in the group, to analyze the read data for identifying the actual polarity of the read data, and to recover the input data from the read data based on the identified actual polarity.
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公开(公告)号：US11972823B2
公开(公告)日：2024-04-30
申请号：US17942143
申请日：2022-09-11
Applicant: Apple Inc.
Inventor： Assaf Shappir
CPC classification number: G11C29/42 , G06F11/1048
Abstract: A controller includes an interface and circuitry. The interface communicates with memory cells arranged in multiple address locations. Storage nodes holding storage values included in the memory cells are accessible using select transistors powered by an adjustable supply voltage. The circuitry reads data units protected by an Error Correction Code (ECC) from the memory cells and decode the ECC of the data units. Upon detecting, using the ECC, that a given data unit read from a given address location contains one or more errors, the circuitry logs an error event specifying at least a time of occurrence associated with the error event and the given address location. The circuitry identifies that the select transistors experience physical degradation due to aging, based on the times of occurrence and address locations logged in the error events, and adjusts the supply voltage provided to the select transistors to compensate for the physical degradation.
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公开(公告)号：US11550657B1
公开(公告)日：2023-01-10
申请号：US17463612
申请日：2021-09-01
Applicant: APPLE INC.
Inventor： Assaf Shappir , Itay Sagron
Abstract: A storage apparatus includes an interface and storage circuitry. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple programming levels. The storage circuitry configured to program data to a first group of multiple memory cells in a number of programming levels larger than two, using a One-Pass Programming (OPP) scheme that results in a first readout reliability level. After programming the data, the storage circuitry is further configured to read the data from the first group, and program the data read from the first group to a second group of the memory cells, in a number of programming levels larger than two, using a Multi-Pass Programming (MPP) scheme that results in a second readout reliability higher than the first reliability level, and reading the data from the second group of the memory cells.
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