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Patent Agency Ranking
公开(公告)号：US11842786B1
公开(公告)日：2023-12-12
申请号：US17852660
申请日：2022-06-29
Applicant: Apple Inc.
Inventor： Nir Tishbi , Ilia Benkovitch , Ruby Mizrahi
CPC classification number: G11C29/50004 , G11C2029/5004
Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells. The processor produces one or more readouts by reading a group of the memory cells using one or more Read Voltages (RVs). Based on the readouts, the processor calculates for a given RV among the RVs a sample of an error signal indicative of a deviation between the given RV and an optimal RV that results in a minimal number of errors in reading the memory cells in the group. The processor applies a filter to the sample of the error signal so as to produce an updated value of the given RV, the filter includes one or more filter taps storing data related to previous samples of the error signal, and reads a second group of the memory cells using the updated value of the given RV.
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公开(公告)号：US20240428877A1
公开(公告)日：2024-12-26
申请号：US18340906
申请日：2023-06-26
Applicant: APPLE INC.
Inventor： Assaf Shappir , Ruby Mizrahi , Nir Tishbi , Itamar Atiya
Abstract: A storage apparatus includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells organized in multiple memory blocks. The storage circuitry is configured to produce a given readout by reading data from a group of the memory cells in a given memory block, using a given read voltage, to calculate a given zeros-ones imbalance level of the given readout, based on the given zeros-ones imbalance level, to check whether the given readout level is zeros-ones balanced or unbalanced in accordance with a balance criterion, and upon detecting that the given readout is zeros-ones unbalanced, mark the given memory block as suspected of being unusable.
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公开(公告)号：US20240006015A1
公开(公告)日：2024-01-04
申请号：US17852660
申请日：2022-06-29
Applicant: Apple Inc.
Inventor： Nir Tishbi , Ilia Benkovitch , Ruby Mizrahi
IPC: G11C29/50
CPC classification number: G11C29/50004 , G11C2029/5004
Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells. The processor produces one or more readouts by reading a group of the memory cells using one or more Read Voltages (RVs). Based on the readouts, the processor calculates for a given RV among the RVs a sample of an error signal indicative of a deviation between the given RV and an optimal RV that results in a minimal number of errors in reading the memory cells in the group. The processor applies a filter to the sample of the error signal so as to produce an updated value of the given RV, the filter includes one or more filter taps storing data related to previous samples of the error signal, and reads a second group of the memory cells using the updated value of the given RV.
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公开(公告)号：US11621048B2
公开(公告)日：2023-04-04
申请号：US17388048
申请日：2021-07-29
Applicant: APPLE INC.
Inventor： Yonathan Tate , Ilia Benkovitch , Michael Jeffet , Nir Tishbi , Roy Roth , Ruby Mizrahi
Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple predefined programming levels. The processor is configured to read an Error Correction Code (ECC) code word from a group of memory cells, via the interface, using multiple read thresholds positioned between adjacent programming levels, for producing multiple readouts that contain respective numbers of errors, to derive from the code word a reference readout that contains no errors, or contains a number of errors smaller than in the code word, to calculate multiple distances between the reference readout and the respective readouts, and set a preferred read threshold based on the calculated distances, and to perform subsequent read operations for retrieving data from the plurality of memory cells, using the preferred read threshold.
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公开(公告)号：US20230031584A1
公开(公告)日：2023-02-02
申请号：US17388048
申请日：2021-07-29
Applicant: APPLE INC.
Inventor： Yonathan Tate , Ilia Benkovitch , Michael Jeffet , Nir Tishbi , Roy Roth , Ruby Mizrahi
Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple predefined programming levels. The processor is configured to read an Error Correction Code (ECC) code word from a group of memory cells, via the interface, using multiple read thresholds positioned between adjacent programming levels, for producing multiple readouts that contain respective numbers of errors, to derive from the code word a reference readout that contains no errors, or contains a number of errors smaller than in the code word, to calculate multiple distances between the reference readout and the respective readouts, and set a preferred read threshold based on the calculated distances, and to perform subsequent read operations for retrieving data from the plurality of memory cells, using the preferred read threshold.
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