-
公开(公告)号：US11520661B1
公开(公告)日：2022-12-06
申请号：US17372568
申请日：2021-07-12
Applicant: Apple Inc.
Inventor： Michael Jeffet , Itay Sagron , Nir Tishbi
Abstract: An apparatus includes a memory and one or more processors. The memory includes multiple memory blocks. The one or more processors are configured to read at least part of data stored in a group of one or more memory blocks, the data including multiple code words of an Error Correction Code (ECC) that is decodable using one or more processing elements selected from among multiple predefined processing elements. The one or more processor are further configured to decode one or more of the code words, and identify one or more of the predefined processing elements that actually participated in decoding the respective code words, and, based on cost-values associated with the identified processing elements, the cost-values are indicative of processing latencies respectively incurred by the identified processing elements, to make a decision of whether or not to refresh the one or more memory blocks in the group.
-
公开(公告)号：US11621048B2
公开(公告)日：2023-04-04
申请号：US17388048
申请日：2021-07-29
Applicant: APPLE INC.
Inventor： Yonathan Tate , Ilia Benkovitch , Michael Jeffet , Nir Tishbi , Roy Roth , Ruby Mizrahi
Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple predefined programming levels. The processor is configured to read an Error Correction Code (ECC) code word from a group of memory cells, via the interface, using multiple read thresholds positioned between adjacent programming levels, for producing multiple readouts that contain respective numbers of errors, to derive from the code word a reference readout that contains no errors, or contains a number of errors smaller than in the code word, to calculate multiple distances between the reference readout and the respective readouts, and set a preferred read threshold based on the calculated distances, and to perform subsequent read operations for retrieving data from the plurality of memory cells, using the preferred read threshold.
-
公开(公告)号：US20230031584A1
公开(公告)日：2023-02-02
申请号：US17388048
申请日：2021-07-29
Applicant: APPLE INC.
Inventor： Yonathan Tate , Ilia Benkovitch , Michael Jeffet , Nir Tishbi , Roy Roth , Ruby Mizrahi
Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple predefined programming levels. The processor is configured to read an Error Correction Code (ECC) code word from a group of memory cells, via the interface, using multiple read thresholds positioned between adjacent programming levels, for producing multiple readouts that contain respective numbers of errors, to derive from the code word a reference readout that contains no errors, or contains a number of errors smaller than in the code word, to calculate multiple distances between the reference readout and the respective readouts, and set a preferred read threshold based on the calculated distances, and to perform subsequent read operations for retrieving data from the plurality of memory cells, using the preferred read threshold.
-
-
Search Results
3
records
(took 0.01 seconds)
