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公开(公告)号：US11962310B1
公开(公告)日：2024-04-16
申请号：US17944215
申请日：2022-09-14
Applicant: Apple Inc.
Inventor： Nir Tishbi , Ilia Benkovitch
CPC classification number: H03L7/0818 , H03L7/091 , H03L7/1075 , H04L7/02 , H04L7/033 , H04L7/0334
Abstract: A receiver includes an interface, a delay line and circuitry. The interface receives data symbols and a clock signal for strobing the data symbols at selected positions. The delay line produces from the clock signal a middle sampling signal, and early and late sampling signals that respectively precedes and succeeds the middle sampling signal. The circuitry samples the data symbols using the middle, early and late sampling signals to produce early and late error signals. Based on the early and late error signals the delay line delays the middle, early and late sampling signals by separate delay values, so as to track both (i) a phase parameter indicative of a deviation between the middle sampling signal and the selected positions of the data symbols, and (ii) a width parameter indicative of a time duration of the data symbols, and to output the data symbols strobed using the middle sampling signal.
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公开(公告)号：US11842786B1
公开(公告)日：2023-12-12
申请号：US17852660
申请日：2022-06-29
Applicant: Apple Inc.
Inventor： Nir Tishbi , Ilia Benkovitch , Ruby Mizrahi
CPC classification number: G11C29/50004 , G11C2029/5004
Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells. The processor produces one or more readouts by reading a group of the memory cells using one or more Read Voltages (RVs). Based on the readouts, the processor calculates for a given RV among the RVs a sample of an error signal indicative of a deviation between the given RV and an optimal RV that results in a minimal number of errors in reading the memory cells in the group. The processor applies a filter to the sample of the error signal so as to produce an updated value of the given RV, the filter includes one or more filter taps storing data related to previous samples of the error signal, and reads a second group of the memory cells using the updated value of the given RV.
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公开(公告)号：US20240006015A1
公开(公告)日：2024-01-04
申请号：US17852660
申请日：2022-06-29
Applicant: Apple Inc.
Inventor： Nir Tishbi , Ilia Benkovitch , Ruby Mizrahi
IPC: G11C29/50
CPC classification number: G11C29/50004 , G11C2029/5004
Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells. The processor produces one or more readouts by reading a group of the memory cells using one or more Read Voltages (RVs). Based on the readouts, the processor calculates for a given RV among the RVs a sample of an error signal indicative of a deviation between the given RV and an optimal RV that results in a minimal number of errors in reading the memory cells in the group. The processor applies a filter to the sample of the error signal so as to produce an updated value of the given RV, the filter includes one or more filter taps storing data related to previous samples of the error signal, and reads a second group of the memory cells using the updated value of the given RV.
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公开(公告)号：US20240428877A1
公开(公告)日：2024-12-26
申请号：US18340906
申请日：2023-06-26
Applicant: APPLE INC.
Inventor： Assaf Shappir , Ruby Mizrahi , Nir Tishbi , Itamar Atiya
Abstract: A storage apparatus includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells organized in multiple memory blocks. The storage circuitry is configured to produce a given readout by reading data from a group of the memory cells in a given memory block, using a given read voltage, to calculate a given zeros-ones imbalance level of the given readout, based on the given zeros-ones imbalance level, to check whether the given readout level is zeros-ones balanced or unbalanced in accordance with a balance criterion, and upon detecting that the given readout is zeros-ones unbalanced, mark the given memory block as suspected of being unusable.
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公开(公告)号：US20230052685A1
公开(公告)日：2023-02-16
申请号：US17399081
申请日：2021-08-11
Applicant: APPLE INC.
Inventor： Yonathan Tate , Nir Tishbi
Abstract: A memory controller includes an interface and a processor. The interface communicates with memory cells organized in multiple Word Lines (WLs). The processor is configured to read a Code Word (CW) of an Error Correction Code (ECC) from a group of multiple memory cells belonging to a target WL, to calculate for a given memory cell (i) a first soft metric, depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL, and (ii) a second soft metric, depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL, to calculate a combined soft metric based on both the first and second soft metrics and assign the combined soft metric to the given memory cell, and to decode the CW based on the combined soft metric, to produce a decoded CW.
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Patent Agency Ranking
公开(公告)号：US11520661B1
公开(公告)日：2022-12-06
申请号：US17372568
申请日：2021-07-12
Applicant: Apple Inc.
Inventor： Michael Jeffet , Itay Sagron , Nir Tishbi
Abstract: An apparatus includes a memory and one or more processors. The memory includes multiple memory blocks. The one or more processors are configured to read at least part of data stored in a group of one or more memory blocks, the data including multiple code words of an Error Correction Code (ECC) that is decodable using one or more processing elements selected from among multiple predefined processing elements. The one or more processor are further configured to decode one or more of the code words, and identify one or more of the predefined processing elements that actually participated in decoding the respective code words, and, based on cost-values associated with the identified processing elements, the cost-values are indicative of processing latencies respectively incurred by the identified processing elements, to make a decision of whether or not to refresh the one or more memory blocks in the group.
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公开(公告)号：US12148496B2
公开(公告)日：2024-11-19
申请号：US17852647
申请日：2022-06-29
Applicant: Apple Inc.
Inventor： Nir Tishbi , Roy Roth , Yonathan Tate
Abstract: A memory controller includes an interface and a processor. The interface is configured to communicate with a plurality of memory cells. The processor is configured to, using multiple Read Thresholds (RTs) positioned between adjacent Programming Voltages (PVs), produce (i) a base parametric model of Threshold Voltage Distributions (TVDs) associated with the PVs, and (ii) auxiliary information that depends on the RTs and on the base parametric model, to read a group of the memory cells using the RTs to produce multiple readouts, the threshold voltages of the memory cells in the group are distributed in accordance with actual TVDs, to derive from the base parametric model an actual parametric model, based on the multiple readouts and on the auxiliary information, and determine a readout parameter based on the actual parametric model, and to perform a read-related operation using the readout parameter.
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8.发明公开公开(公告)号：US20240006014A1
公开(公告)日：2024-01-04
申请号：US17852647
申请日：2022-06-29
Applicant: Apple Inc.
Inventor： Nir Tishbi , Roy Roth , Yonathan Tate
CPC classification number: G11C29/50004 , G11C7/1069 , G11C2029/5004
Abstract: A memory controller includes an interface and a processor. The interface is configured to communicate with a plurality of memory cells. The processor is configured to, using multiple Read Thresholds (RTs) positioned between adjacent Programming Voltages (PVs), produce (i) a base parametric model of Threshold Voltage Distributions (TVDs) associated with the PVs, and (ii) auxiliary information that depends on the RTs and on the base parametric model, to read a group of the memory cells using the RTs to produce multiple readouts, the threshold voltages of the memory cells in the group are distributed in accordance with actual TVDs, to derive from the base parametric model an actual parametric model, based on the multiple readouts and on the auxiliary information, and determine a readout parameter based on the actual parametric model, and to perform a read-related operation using the readout parameter.
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公开(公告)号：US11874736B2
公开(公告)日：2024-01-16
申请号：US17399081
申请日：2021-08-11
Applicant: APPLE INC.
Inventor： Yonathan Tate , Nir Tishbi
CPC classification number: G06F11/1068 , G11C16/04 , G11C29/52 , H03M13/45
Abstract: A memory controller includes an interface and a processor. The interface communicates with memory cells organized in multiple Word Lines (WLs). The processor is configured to read a Code Word (CW) of an Error Correction Code (ECC) from a group of multiple memory cells belonging to a target WL, to calculate for a given memory cell (i) a first soft metric, depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL, and (ii) a second soft metric, depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL, to calculate a combined soft metric based on both the first and second soft metrics and assign the combined soft metric to the given memory cell, and to decode the CW based on the combined soft metric, to produce a decoded CW.
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公开(公告)号：US11847342B2
公开(公告)日：2023-12-19
申请号：US17512712
申请日：2021-10-28
Applicant: Apple Inc.
Inventor： Nir Tishbi
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0644 , G06F3/0679
Abstract: An apparatus for data storage, includes circuitry and a plurality of memory cells. The circuitry is configured to store data in a group of multiple memory cells by writing multiple respective input storage values to the memory cells in the group, to read respective output storage values from the memory cells in the group after storing the data, to generate for the output storage values multiple respective confidence levels, to produce composite data that includes the output storage values, to test a predefined condition that depends on the confidence levels, upon detecting that the condition is met, to compress the confidence levels to produce compressed soft data, and include the compressed soft data in the composite data, and to transfer the composite data over an interface to a memory controller.
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