公开(公告)号：US20200091933A1

公开(公告)日：2020-03-19

申请号：US16130003

申请日：2018-09-13

Applicant: Apple Inc.

Inventor： Yonathan Tate ,  Naftali Sommer ,  Asaf Landau ,  Armand Chocron

IPC: H03M13/11 ,  H03M13/25 ,  H03M13/29

Abstract: An apparatus includes an interface and a decoder. The interface is configured to receive a code word, produced in accordance with an Error Correction Code (ECC) represented by a set of parity check equations. The code word includes a data part and a redundancy part, and contains one or more errors. The decoder is configured to hold a definition of a partial subgroup of the parity check equations that, when satisfied, indicate that the data part is error-free with a likelihood of at least a predefined threshold, to decode the code word by performing an iterative decoding process on the parity check equations, so as to correct the errors, and during the iterative decoding process, to estimate whether the data part is error-free based only on the partial subgroup of the parity check equations, and if the data part is estimated to be error-free, terminate the iterative decoding process.

公开(公告)号：US20160094245A1

公开(公告)日：2016-03-31

申请号：US14499284

申请日：2014-09-29

Applicant: APPLE INC.

Inventor： Asaf Landau ,  Tomer Ish-Shalom ,  Yonathan Tate

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/116 ,  H03M13/1102 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/15 ,  H03M13/271 ,  H03M13/616 ,  H03M13/6552 ,  H03M13/6555 ,  H04L1/0057

Abstract: A decoder includes variable-node circuitry, check-node circuitry and a Message Passing (MP) module, which includes multiple configurable partial cyclic shifters that each supports only a partial subset of shift values out of a full range of shift values 0 . . . L−1. The variable-node circuitry and check-node circuitry are configured to exchange messages with one another in accordance with a parity check matrix that represents a respective Quasi-Cyclic (QC)-Low Density Parity Check (LDPC) Error Correcting Code (ECC) and that includes L-by-L sub-matrices, and to process the exchanged messages to decode a given code word that was encoded using the QC-LDPC ECC. The MP module is configured to schedule the variable-node circuitry and check-node circuitry that are interconnected in accordance with a respective sub-matrix to exchange L messages simultaneously by assigning a given partial cyclic shifter to shift the L messages cyclically a number of positions that depends on a structure of the respective sub-matrix.

Abstract translation: 解码器包括可变节点电路，校验节点电路和消息传递（MP）模块，消息传递（MP）模块包括多个可配置的部分循环移位器，每个移位器仅支持移位值0的全范围内的移位值的部分子集。 。 。 L-1。 可变节点电路和校验节点电路被配置为根据表示相应的准循环（QC） - 低密度奇偶校验（LDPC）纠错码（ECC）的奇偶校验矩阵和彼此之间的交换消息 其包括L乘L子矩阵，并处理所交换的消息以解码使用QC-LDPC ECC编码的给定码字。 MP模块被配置为根据相应的子矩阵来调度互连的可变节点电路和校验节点电路，以通过分配给定的部分循环移位器来周期性地移动L个消息来同时交换L个消息 这取决于相应子矩阵的结构。

公开(公告)号：US20240022262A1

公开(公告)日：2024-01-18

申请号：US17863425

申请日：2022-07-13

Applicant: Apple Inc.

Inventor： Roy Roth ,  Yonathan Tate

IPC: H03M13/29 ,  H03M13/43 ,  H03M13/11

CPC classification number: H03M13/2948 ,  H03M13/43 ,  H03M13/1108

Abstract: A decoder includes circuitry and multiple Variable-Node Circuits (VNCs). The VNCs individually hold one or more variables of an Error Correction Code (ECC) that is representable by a plurality of check equations defined over the variables. The circuitry is configured to receive a code word including variables having m-bit values that was encoded using the ECC, to further receive reliability levels assigned respectively to the variables, to decode the code word by applying to the code word a sequence of iterations, including deciding in a given iteration whether a given VNC is to be processed or skipped in that iteration, depending on the reliability levels assigned to the variables of the given VNC, and, when the given VNC is selected for processing, to make a decision whether or not to update one or more of the variables of the given VNC, and to apply the decision by the given VNC.

公开(公告)号：US10998920B1

公开(公告)日：2021-05-04

申请号：US16801249

申请日：2020-02-26

Applicant: Apple Inc.

Inventor： Yonathan Tate ,  Eli Yazovitsky ,  Michael Tsohar

IPC: H03M13/15 ,  H03M13/39 ,  H03M13/11 ,  G11C29/44 ,  H03M13/43 ,  G06F11/07 ,  G11C29/42

Abstract: A controller includes an interface and circuitry. The interface is coupled to multiple memory cells. The circuitry stores a code word in a group of the memory cells, reads the code word using different thresholds to produce first and second readouts, and checks whether approximating each of first and second numbers of readout errors based on syndrome weights is valid. In response to determining that only the approximation of the second number of errors is valid, the circuitry produces a combined readout by replacing a portion of the bits in the second readout with corresponding bits of the first readout, calculates an enhanced syndrome weight for the combined readout and estimates the first number of errors based on the enhanced syndrome weight. The circuitry improves readout performance from at least the group of the memory cells using at least one of the estimated first and second numbers of errors.

公开(公告)号：US10388394B2

公开(公告)日：2019-08-20

申请号：US15658430

申请日：2017-07-25

Applicant: Apple Inc.

Inventor： Yonathan Tate ,  Tomer Ish-Shalom

IPC: G11C29/00 ,  G11C29/42 ,  G06F11/10 ,  G11C29/44

Abstract: A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to read from a group of the memory cells a code word encoded using an Error Correction Code (ECC), by sensing the memory cells using at least first and second read thresholds for producing respective first and second readouts, to calculate, based on at least one of the first and second readouts, (i) a syndrome weight that is indicative of an actual number of errors contained in the code word, and (ii) a mid-zone count of the memory cells for which the first readout differs from the second readout, and, to evaluate a performance measure for the memory cells, based on the calculated syndrome weight and mid-zone count.

公开(公告)号：US20230052685A1

公开(公告)日：2023-02-16

申请号：US17399081

申请日：2021-08-11

Applicant: APPLE INC.

Inventor： Yonathan Tate ,  Nir Tishbi

IPC: G06F11/10 ,  G11C16/04 ,  H03M13/45 ,  G11C29/52

Abstract: A memory controller includes an interface and a processor. The interface communicates with memory cells organized in multiple Word Lines (WLs). The processor is configured to read a Code Word (CW) of an Error Correction Code (ECC) from a group of multiple memory cells belonging to a target WL, to calculate for a given memory cell (i) a first soft metric, depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL, and (ii) a second soft metric, depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL, to calculate a combined soft metric based on both the first and second soft metrics and assign the combined soft metric to the given memory cell, and to decode the CW based on the combined soft metric, to produce a decoded CW.

公开(公告)号：US10382069B2

公开(公告)日：2019-08-13

申请号：US14823061

申请日：2015-08-11

Applicant: APPLE INC.

Inventor： Moti Teitel ,  Tomer Ish-Shalom ,  Yonathan Tate

IPC: H03M13/11 ,  H03M13/00

Abstract: A method for data encoding includes receiving a data vector to be encoded into a code word in accordance with a code defined by a parity-check matrix H. An intermediate vector s is produced by multiplying the data vector by a data sub-matrix Hs of the parity-check matrix H. A parity part of the code word is derived by applying a sequence of operations to the intermediate vector s based on a decomposition of a parity sub-matrix Hp of the matrix H using matrices A, C, U and V, in which decomposition A is a block triangular matrix that has the same size as Hp, C is matrix that is smaller than Hp, and the matrices U and V are placement matrices that are selected so that A, C, U and V satisfy a matrix equation Hp=A+UCV.

公开(公告)号：US20190207630A1

公开(公告)日：2019-07-04

申请号：US15856107

申请日：2017-12-28

Applicant: Apple Inc.

Inventor： Yonathan Tate ,  Tomer Ish-Shalom

IPC: H03M13/37 ,  H03M13/39 ,  H03M13/43 ,  H03M13/11

CPC classification number: H03M13/3746 ,  H03M13/11 ,  H03M13/1108 ,  H03M13/1131 ,  H03M13/39 ,  H03M13/43

Abstract: A decoder includes multiple variable-node circuits and logic circuitry. The variable-node circuits hold variables of an Error Correction Code (ECC), defined by a set of check equations over multiple variables corresponding to the variable-node circuits. The logic circuitry is configured to receive a code word encoded using the ECC, to hold, prior to decoding in a sequence of iterations, a scheduling scheme that specifies, for each iteration, whether each of the variable-node circuits is to be processed or skipped in that iteration, to perform the iterations in the sequence, including selecting for processing, in each iteration, only variable-node circuits specified for processing in that iteration, to determine for each selected variable-node circuit, a count of unsatisfied check equations in which the respective variable participates, and to make a decision on flipping a binary value of the variable based on the count and apply the decision by the respective variable-node circuit.

公开(公告)号：US09697075B2

公开(公告)日：2017-07-04

申请号：US14847037

申请日：2015-09-08

Applicant: Apple Inc.

Inventor： Yonathan Tate ,  Barak Baum ,  Moti Teitel

IPC: G11C16/04 ,  G11C29/00 ,  G06F11/10 ,  G11C7/14 ,  G11C11/56 ,  G11C16/28

CPC classification number: G06F11/1068 ,  G11C7/14 ,  G11C11/5642 ,  G11C16/28

Abstract: A method includes storing data encoded with an ECC in a group of memory cells by writing respective storage values to the memory cells. Multiple sets of readout results are read from the memory cells by comparing the storage values to one or more threshold combinations, each including multiple read thresholds. A plurality of partial syndromes of the ECC is computed, each partial syndrome computed over the readout results that were read using a respective threshold combination. A respective syndrome is calculated for each threshold combination, in at least a subset of all possible threshold combinations, based on one or more of the partial syndromes associated with that threshold combination. A preferred threshold combination is selected, from among the threshold combinations, for which a weight of the respective syndrome is minimal, by processing less than all the partial syndromes associated with all the possible threshold combinations.

公开(公告)号：US20170068591A1

公开(公告)日：2017-03-09

申请号：US14847037

申请日：2015-09-08

Applicant: Apple Inc.

Inventor： Yonathan Tate ,  Barak Baum ,  Moti Teitel

IPC: G06F11/10 ,  G11C29/52 ,  G11C16/26 ,  G11C11/56 ,  G11C16/10

CPC classification number: G06F11/1068 ,  G11C7/14 ,  G11C11/5642 ,  G11C16/28

Abstract: A method includes storing data encoded with an ECC in a group of memory cells by writing respective storage values to the memory cells. Multiple sets of readout results are read from the memory cells by comparing the storage values to one or more threshold combinations, each including multiple read thresholds. A plurality of partial syndromes of the ECC is computed, each partial syndrome computed over the readout results that were read using a respective threshold combination. A respective syndrome is calculated for each threshold combination, in at least a subset of all possible threshold combinations, based on one or more of the partial syndromes associated with that threshold combination. A preferred threshold combination is selected, from among the threshold combinations, for which a weight of the respective syndrome is minimal, by processing less than all the partial syndromes associated with all the possible threshold combinations.

Abstract translation: 一种方法包括通过将相应的存储值写入存储器单元来将通过ECC编码的数据存储在一组存储器单元中。 通过将存储值与一个或多个阈值组合进行比较，每组包括多个读取阈值，从存储器单元读取多组读出结果。 计算出ECC的多个部分综合征，使用相应的阈值组合读取的读出结果计算每个部分校正子。 基于与该阈值组合相关联的一个或多个部分综合征，在所有可能的阈值组合的至少一个子集中针对每个阈值组合计算相应的综合征。 通过处理小于与所有可能的阈值组合相关联的所有部分综合征，从相应综合征的权重最小的阈值组合中选择优选阈值组合。