公开(公告)号：US20170163288A1

公开(公告)日：2017-06-08

申请号：US14961913

申请日：2015-12-08

Applicant: Apple Inc.

Inventor： Yonathan Tate ,  Asaf Landau ,  Micha Anholt

IPC: H03M13/11 ,  G06F11/07

CPC classification number: H03M13/1131 ,  G06F11/0727 ,  G06F11/076 ,  H03M13/1128 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116

Abstract: A decoder includes an interface and circuitry. The interface is configured to receive a code word that was encoded using a Quasi-Cyclic Low Density Parity Check (QC-LDPC) Error Correcting Code (ECC) represented by multiple check equations that are defined over multiple variables. The circuitry is configured to decode the code word by iteratively processing multiple layers that each includes a respective subset of the variables of the code word, and producing per each layer one or more count updates, and to generate a total number of errors corrected over the entire code word by accumulating the count updates.

公开(公告)号：US09853661B2

公开(公告)日：2017-12-26

申请号：US14961913

申请日：2015-12-08

Applicant: Apple Inc.

Inventor： Yonathan Tate ,  Asaf Landau ,  Micha Anholt

IPC: H04L1/00 ,  H03M13/11 ,  G06F11/07

CPC classification number: H03M13/1131 ,  G06F11/0727 ,  G06F11/076 ,  H03M13/1128 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116

Abstract: A decoder includes an interface and circuitry. The interface is configured to receive a code word that was encoded using a Quasi-Cyclic Low Density Parity Check (QC-LDPC) Error Correcting Code (ECC) represented by multiple check equations that are defined over multiple variables. The circuitry is configured to decode the code word by iteratively processing multiple layers that each includes a respective subset of the variables of the code word, and producing per each layer one or more count updates, and to generate a total number of errors corrected over the entire code word by accumulating the count updates.

公开(公告)号：US09595977B2

公开(公告)日：2017-03-14

申请号：US14499284

申请日：2014-09-29

Applicant: APPLE INC.

Inventor： Asaf Landau ,  Tomer Ish-Shalom ,  Yonathan Tate

IPC: H03M13/11 ,  H03M13/27 ,  H04L1/00 ,  H03M13/00 ,  H03M13/15

CPC classification number: H03M13/116 ,  H03M13/1102 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/15 ,  H03M13/271 ,  H03M13/616 ,  H03M13/6552 ,  H03M13/6555 ,  H04L1/0057

Abstract: A decoder includes variable-node circuitry, check-node circuitry and a Message Passing (MP) module, which includes multiple configurable partial cyclic shifters that each supports only a partial subset of shift values out of a full range of shift values 0 . . . L−1. The variable-node circuitry and check-node circuitry are configured to exchange messages with one another in accordance with a parity check matrix that represents a respective Quasi-Cyclic (QC)-Low Density Parity Check (LDPC) Error Correcting Code (ECC) and that includes L-by-L sub-matrices, and to process the exchanged messages to decode a given code word that was encoded using the QC-LDPC ECC. The MP module is configured to schedule the variable-node circuitry and check-node circuitry that are interconnected in accordance with a respective sub-matrix to exchange L messages simultaneously by assigning a given partial cyclic shifter to shift the L messages cyclically a number of positions that depends on a structure of the respective sub-matrix.

Abstract translation: 解码器包括可变节点电路，校验节点电路和消息传递（MP）模块，消息传递（MP）模块包括多个可配置的部分循环移位器，每个移位器仅支持移位值0的全范围内的移位值的部分子集。 。 。 L-1。 可变节点电路和校验节点电路被配置为根据表示相应的准循环（QC） - 低密度奇偶校验（LDPC）纠错码（ECC）的奇偶校验矩阵和彼此之间的交换消息 其包括L乘L子矩阵，并处理所交换的消息以解码使用QC-LDPC ECC编码的给定码字。 MP模块被配置为根据相应的子矩阵来调度互连的可变节点电路和校验节点电路，以通过分配给定的部分循环移位器来周期性地移动L个消息来同时交换L个消息 这取决于相应子矩阵的结构。

公开(公告)号：US20200091933A1

公开(公告)日：2020-03-19

申请号：US16130003

申请日：2018-09-13

Applicant: Apple Inc.

Inventor： Yonathan Tate ,  Naftali Sommer ,  Asaf Landau ,  Armand Chocron

IPC: H03M13/11 ,  H03M13/25 ,  H03M13/29

Abstract: An apparatus includes an interface and a decoder. The interface is configured to receive a code word, produced in accordance with an Error Correction Code (ECC) represented by a set of parity check equations. The code word includes a data part and a redundancy part, and contains one or more errors. The decoder is configured to hold a definition of a partial subgroup of the parity check equations that, when satisfied, indicate that the data part is error-free with a likelihood of at least a predefined threshold, to decode the code word by performing an iterative decoding process on the parity check equations, so as to correct the errors, and during the iterative decoding process, to estimate whether the data part is error-free based only on the partial subgroup of the parity check equations, and if the data part is estimated to be error-free, terminate the iterative decoding process.

公开(公告)号：US10193574B1

公开(公告)日：2019-01-29

申请号：US15158620

申请日：2016-05-19

Applicant: APPLE INC.

Inventor： Moti Teitel ,  Asaf Landau ,  Tomer Ish-Shalom

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/11 ,  H04L1/00 ,  H03M13/29 ,  G11B20/18 ,  G06F11/10

Abstract: An apparatus includes an interface, main and secondary processing modules, and circuitry. The interface is configured to receive input data to be processed in accordance with a GLDPC code defined by a parity-check-matrix including multiple sub-matrices, each sub-matrix including a main diagonal and one or more secondary diagonals, and each of the main and secondary diagonals includes N respective block matrices. The main processing module is configured to calculate N first partial syndromes based on the input data and on the block matrices of the main diagonals. The secondary processing module is configured to calculate N second partial syndromes based on the input data and on the block matrices of the secondary diagonals. The circuitry is configured to produce N syndromes by respectively combining the N first partial syndromes with the N second partial syndromes, and to encode or decode the input data, based on the N syndromes.

公开(公告)号：US20160094245A1

公开(公告)日：2016-03-31

申请号：US14499284

申请日：2014-09-29

Applicant: APPLE INC.

Inventor： Asaf Landau ,  Tomer Ish-Shalom ,  Yonathan Tate

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/116 ,  H03M13/1102 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/15 ,  H03M13/271 ,  H03M13/616 ,  H03M13/6552 ,  H03M13/6555 ,  H04L1/0057

Abstract: A decoder includes variable-node circuitry, check-node circuitry and a Message Passing (MP) module, which includes multiple configurable partial cyclic shifters that each supports only a partial subset of shift values out of a full range of shift values 0 . . . L−1. The variable-node circuitry and check-node circuitry are configured to exchange messages with one another in accordance with a parity check matrix that represents a respective Quasi-Cyclic (QC)-Low Density Parity Check (LDPC) Error Correcting Code (ECC) and that includes L-by-L sub-matrices, and to process the exchanged messages to decode a given code word that was encoded using the QC-LDPC ECC. The MP module is configured to schedule the variable-node circuitry and check-node circuitry that are interconnected in accordance with a respective sub-matrix to exchange L messages simultaneously by assigning a given partial cyclic shifter to shift the L messages cyclically a number of positions that depends on a structure of the respective sub-matrix.

Abstract translation: 解码器包括可变节点电路，校验节点电路和消息传递（MP）模块，消息传递（MP）模块包括多个可配置的部分循环移位器，每个移位器仅支持移位值0的全范围内的移位值的部分子集。 。 。 L-1。 可变节点电路和校验节点电路被配置为根据表示相应的准循环（QC） - 低密度奇偶校验（LDPC）纠错码（ECC）的奇偶校验矩阵和彼此之间的交换消息 其包括L乘L子矩阵，并处理所交换的消息以解码使用QC-LDPC ECC编码的给定码字。 MP模块被配置为根据相应的子矩阵来调度互连的可变节点电路和校验节点电路，以通过分配给定的部分循环移位器来周期性地移动L个消息来同时交换L个消息 这取决于相应子矩阵的结构。