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    Nonvolatile semiconductor memory device
    2.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US4813018A

    公开(公告)日：1989-03-14

    申请号：US125540

    申请日：1987-11-25

    Applicant: Kazuo Kobayashi ,  Yasushi Terada ,  Takeshi Nakayama

    Inventor： Kazuo Kobayashi ,  Yasushi Terada ,  Takeshi Nakayama

    IPC: G11C17/00 ,  G11C14/00 ,  G11C16/04 ,  G11C7/00

    CPC classification number: G11C14/00

    Abstract: A nonvolatile semiconductor memory device comprises a random access memory (RAM) and an electrically programmable and erasable read only memory (EEPROM). Since a capacitance (106) is formed between a control gate (103) and a drain (102) of a memory transistor, and a source of the memory transistor is rendered to be floating in the RAM write and read operation and in the EEPROM write operation and is supplied with a finite potential in EEPROM read operation, the operation of nonvolatile memory is achieved. A sense amplifier (15, 16) is amplified the potential difference between a bit line (BL) and a control gate line (CGL) is both memory operation and latches the input data in both write operation, such that the potential of the BL and the CGL are determined low or high potential. Besides in the EEPROM write operation, after latching the input data in the sense amplifier, a nonvolatile program is started such that a BL or a CGL is pumped up to program voltage (15-20 V). In the EEPROM read operation, a BL and a CGL are pre-changed in a different potential (BL CGL). After that, the sense amplifier is activated and the EEPROM data is read out.

    Abstract translation: 非易失性半导体存储器件包括随机存取存储器（RAM）和电可编程和可擦除只读存储器（EEPROM）。 由于在存储晶体管的控制栅极（103）和漏极（102）之间形成电容（106），并且存储晶体管的源极被浮置在RAM写入和读取操作中以及EEPROM写入 在EEPROM读操作中提供有限电位，实现非易失性存储器的操作。 读出放大器（15,16）被放大，位线（BL）和控制栅极线（CGL）之间的电位差都是存储器操作，并且在两个写操作中锁存输入数据，使得BL和 CGL被确定为低电位或高电位。 除了EEPROM写入操作之外，在将读出放大器中的输入数据锁存之后，启动非易失性程序，使BL或CGL被泵送到编程电压（15-20V）。 在EEPROM读取操作中，BL和CGL在相同电位（BL = CGL）均衡之后被预先改变为不同的电位（BL CGL）。 之后，激活读出放大器并读出EEPROM数据。

    Nonvolatile semiconductor memory device
    3.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US4760556A

    公开(公告)日：1988-07-26

    申请号：US911431

    申请日：1986-09-25

    Applicant: Mikio Deguchi ,  Kazuyasu Fujishima ,  Yasushi Terada

    Inventor： Mikio Deguchi ,  Kazuyasu Fujishima ,  Yasushi Terada

    IPC: G11C17/00 ,  G11C11/404 ,  G11C14/00 ,  G11C16/04 ,  G11C11/40

    CPC classification number: G11C14/00

    Abstract: Each of the memory cells forming a nonvolatile RAM comprises one floating-gate transistor and one capacitor. When the power source is turned on, storage of information is performed according to the amount of electric charge stored in each capacitor. When the power source is turned off, nonvolatile storage of information is performed according to the level of the threshold voltage of each floating-gate transistor.

    Abstract translation: 形成非易失性RAM的每个存储单元包括一个浮栅晶体管和一个电容器。 当电源接通时，根据每个电容器中存储的电荷量进行信息存储。 当电源关闭时，根据每个浮栅晶体管的阈值电压的电平执行信息的非易失性存储。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4691216A

    公开(公告)日：1987-09-01

    申请号：US811881

    申请日：1985-12-20

    Applicant: Yasushi Terada ,  Takeshi Nakayama

    Inventor： Yasushi Terada ,  Takeshi Nakayama

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

    CPC classification number: G11C16/30

    Abstract: A semiconductor memory device in which an output of a reference voltage generator for defining the height of a programming high-voltage pulse is changed according to the thickness of a tunnel oxide film and/or a floating gate oxide film of a memory transistor so that a shift amount of a threshold voltage of an EEPROM is maintained at a constant value if the thickness of the oxide films is deviated from a designed value.

    Abstract translation: 一种半导体存储器件，其中用于限定编程高电压脉冲的高度的参考电压发生器的输出根据存储晶体管的隧道氧化物膜和/或浮栅氧化膜的厚度而改变，使得 如果氧化膜的厚度偏离设计值，则EEPROM的阈值电压的移位量保持恒定值。

    Non-volatile semiconductor memory device
    7.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5554868A

    公开(公告)日：1996-09-10

    申请号：US300877

    申请日：1994-09-06

    Applicant: Masanori Hayashikoshi ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi

    Inventor： Masanori Hayashikoshi ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi

    IPC: G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/34 ,  H01L29/788

    CPC classification number: G11C16/3404 ,  G11C16/3409

    Abstract: There is a case where a memory cell brought to an over-erase (depletion) state if the erasing time is too long, for example, in an electrically erasable non-volatile semiconductor memory device. In this case, the transistor constituting the memory cell is always in ON state and causes erroneous operation. Therefore, it is detected whether there is any memory cell in the over-erase state or not after erasing in each memory cell, and if any memory cell is detected being in the over-erase state, tunnel writing is performed in each memory cell. Specifically, electrons are injected into the floating gate of the transistor constituting each memory cell by a tunnel phenomenon. This causes the memory cell in the over-erase state to recover to a normal state. Detection of the over-erase state and recovery from it are performed by an over-erase correcting circuit 72.

    Abstract translation: 如果擦除时间过长，例如在电可擦除非易失性半导体存储器件中存在存储器单元进入过擦除（耗尽）状态的情况。 在这种情况下，构成存储单元的晶体管总是处于导通状态并导致错误的操作。 因此，在每个存储单元中擦除之后检测是否存在处于过擦除状态的任何存储单元，并且如果检测到任何存储单元处于过擦除状态，则在每个存储单元中进行隧道写入。 具体地，电子通过隧道现象注入构成每个存储单元的晶体管的浮置栅极。 这使得处于过擦除状态的存储单元恢复到正常状态。 通过过擦除校正电路72执行过擦除状态和从其恢复的检测。

    Electrically erasable and programmable non-volatile memory device and a method of operating the same
    8.
    发明授权
    Electrically erasable and programmable non-volatile memory device and a method of operating the same 失效
    电可擦除和可编程的非易失性存储器件及其操作方法

    公开(公告)号：US5428568A

    公开(公告)日：1995-06-27

    申请号：US933436

    申请日：1992-08-20

    Applicant: Shinichi Kobayashi ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya

    Inventor： Shinichi Kobayashi ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya

    IPC: G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C11/34

    CPC classification number: G11C16/3409 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445 ,  G11C16/3459

    Abstract: In a programming mode of operation of a flash type non-volatile semiconductor memory device, an erase voltage pulse is applied a memory cell to bring the memory cell into an erased state. Then, an after-erase writing operation is executed for a memory cell having a threshold voltage lower than a predetermined threshold voltage under the condition of small change in threshold voltage. Alternatively, an erase voltage pulse is applied only to a memory cell having a threshold voltage greater than a predetermined threshold voltage to carry out erasing. Also, after a memory cell is brought to a depletion state by application of an erase voltage pulse, data writing of "0" and "1" is carried out by injection of electrons into the floating gate. The electron injection rate to the floating gate for writing data "0" is set to be greater than that for writing data "1". The state of storing data "1" corresponds to an erase state. According to this scheme, an excessively erased memory cell does not exist and the distribution range of threshold voltage can be reduced. Furthermore, the reprogramming time period for a memory cell data can be carried out in a short time.

    Abstract translation: 在闪存型非易失性半导体存储器件的编程操作模式中，擦除电压脉冲被施加到存储器单元以使存储单元进入擦除状态。 然后，在阈值电压变化小的条件下，对具有低于预定阈值电压的阈值电压的存储单元执行擦除后写入操作。 或者，擦除电压脉冲仅施加到具有大于预定阈值电压的阈值电压的存储器单元以执行擦除。 此外，在通过施加擦除电压脉冲将存储单元置于耗尽状态之后，通过向浮置栅极注入电子来执行“0”和“1”的数据写入。 写入数据“0”的浮动栅极的电子注入速率被设定为大于写入数据“1”的电子注入速率。 存储数据“1”的状态对应于擦除状态。 根据该方案，不存在过度擦除的存储单元，并且可以减小阈值电压的分布范围。 此外，存储单元数据的重新编程时间段可以在短时间内进行。

    Nonvolatile semiconductor memory device and data erasing method thereof
    9.
    发明授权
    Nonvolatile semiconductor memory device and data erasing method thereof 失效
    非易失性半导体存储器件及其数据擦除方法

    公开(公告)号：US5297096A

    公开(公告)日：1994-03-22

    申请号：US711547

    申请日：1991-06-07

    Applicant: Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Tomoshi Futatsuya

    Inventor： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Tomoshi Futatsuya

    IPC: G11C17/00 ,  G11C16/02 ,  G11C16/14 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

    CPC classification number: G11C16/14 ,  G11C16/16

    Abstract: A flash EEPROM including a memory cell array divided into first and second blocks. Erase pulse applying circuits for applying erase pulses to memory cells and erase verifying circuits for erase-verifying the memory cells are provided one for each of those two blocks. The erase pulse applying circuit and the erase verifying circuit provided corresponding to the first block operate separately from the erase pulse applying circuit and the erase verifying circuit provided corresponding to the second block. The erase pulse applying circuits are each controlled by their corresponding erase verifying circuits. That is, each erase verifying circuit enables its corresponding erase pulse applying circuit only when detecting a memory cell in which a data erase is incomplete in the corresponding block.

    Abstract translation: 一种快闪EEPROM，包括分为第一和第二块的存储单元阵列。 为这两个块中的每一个提供擦除用于向存储单元施加擦除脉冲的脉冲施加电路和用于擦除验证存储单元的擦除验证电路。 对应于第一块设置的擦除脉冲施加电路和擦除验证电路与擦除脉冲施加电路和对应于第二块设置的擦除验证电路分开工作。 擦除脉冲施加电路各自由其相应的擦除验证电路控制。 也就是说，每个擦除验证电路仅在检测到相应块中的数据擦除不完整的存储单元时才能使其相应的擦除脉冲施加电路。

    Divided word line type non-volatile semiconductor memory device
    10.
    发明授权
    Divided word line type non-volatile semiconductor memory device 失效
    分字线型非易失性半导体存储器件

    公开(公告)号：US5132928A

    公开(公告)日：1992-07-21

    申请号：US501703

    申请日：1990-03-30

    Applicant: Masanori Hayashikoshi ,  Yasushi Terada ,  Kazuo Kobayashi ,  Takeshi Nakayama ,  Yoshikazu Miyawaki

    Inventor： Masanori Hayashikoshi ,  Yasushi Terada ,  Kazuo Kobayashi ,  Takeshi Nakayama ,  Yoshikazu Miyawaki

    IPC: G11C17/00 ,  G06F11/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C29/00 ,  G11C29/42

    CPC classification number: G06F11/1008 ,  G06F11/1076 ,  G11C16/08 ,  G11C16/26

    Abstract: An electrically programmable non-volatile semiconductor memory device includes a plurality of internal data transmission lines. Data communication between memory cells and the internal data transmission lines is performed for a byte of data having a plurality of bits. Each of the word lines includes a plurality of divided auxiliary word lines in association with the internal data transmission lines. Those memory cells for each word line that are to be connected to the same internal data transmission line are connected to one auxiliary word line. Only one of a plurality of memory cells connected to one auxiliary word line is connected to an internal data transmission line in operation. Therefore, a plurality of the memory cells connected to different auxiliary word lines, are connected in parallel to a plurality of the internal data transmission lines. According to this arrangement, the effect of word line destruction occasionally caused in one auxiliary word line is not extended to other auxiliary word lines, so that the damaged auxiliary word line can be repaired by the use of an error correction detection code.

    Abstract translation: 电可编程非易失性半导体存储器件包括多个内部数据传输线。 对于具有多个位的数据的字节执行存储器单元与内部数据传输线之间的数据通信。 每个字线包括与内部数据传输线相关联的多个划分的辅助字线。 要连接到同一内部数据传输线的每个字线的那些存储单元连接到一个辅助字线。 连接到一个辅助字线的多个存储单元中只有一个连接到操作中的内部数据传输线。 因此，连接到不同辅助字线的多个存储单元并联连接到多个内部数据传输线。 根据这种布置，偶然地在一个辅助字线中引起的字线破坏的影响不会扩展到其他辅助字线，从而可以通过使用纠错检测码修复损坏的辅助字线。

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